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Itanium

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</style><div role="note" class="hatnote navigation-not-searchable">Further information on the instruction set architecture, not chip implementations: <a href="IA-64" title="IA-64">IA-64</a></div>

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</style><table class="infobox"><caption class="infobox-title">Itanium</caption><tbody><tr><td colspan="2" class="infobox-image"></td></tr><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">June 2001 (2001-06)<a href="#cite_note-6">[a]</a></td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">January 30, 2020 (2020-01-30)<a href="#cite_note-theend-1">[1]</a></td></tr><tr><th scope="row" class="infobox-label">Marketed by</th><td class="infobox-data"><a href="Intel" title="Intel">Intel</a></td></tr><tr><th scope="row" class="infobox-label">Designed by</th><td class="infobox-data">Intel Hewlett-Packard</td></tr><tr><th scope="row" class="infobox-label">Common manufacturer</th><td class="infobox-data"><style data-mw-deduplicate="TemplateStyles:r1126788409">

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</style><div class="plainlist"><ul><li>Intel</li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="Central_processing_unit" title="Central processing unit">CPU</a> <a href="Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">733 MHz to 2.66 GHz</td></tr><tr><th scope="row" class="infobox-label"><a href="Front-side_bus" title="Front-side bus">FSB</a> speeds</th><td class="infobox-data">266 MT/s to 667 MT/s</td></tr><tr><th scope="row" class="infobox-label"><a href="Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">QPI</a> speeds</th><td class="infobox-data">4.8 GT/s to 6.4 GT/s</td></tr><tr><th scope="row" class="infobox-label">Data width</th><td class="infobox-data">64 bits</td></tr><tr><th scope="row" class="infobox-label">Address width</th><td class="infobox-data">64 bits</td></tr><tr><th scope="row" class="infobox-label">Virtual address width</th><td class="infobox-data">64 bits</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L1 <a href="CPU_cache" title="CPU cache">cache</a></th><td class="infobox-data">Up to 32 KB per core (data) Up to 32 KB per core (instructions)</td></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">Up to 256 KB per core (data) Up to 1 MB per core (instructions)</td></tr><tr><th scope="row" class="infobox-label">L3 cache</th><td class="infobox-data">Up to 32 MB</td></tr><tr><th scope="row" class="infobox-label">L4 cache</th><td class="infobox-data">32 MB (Hondo only)</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label">Application</th><td class="infobox-data">High-end/<a href="Mission_critical" title="Mission critical">mission critical servers</a> <a href="High_performance_computing" class="mw-redirect" title="High performance computing">High performance computing</a> High-end workstations</td></tr><tr><th scope="row" class="infobox-label"><a href="Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data">180 nm to 32 nm</td></tr><tr><th scope="row" class="infobox-label"><a href="Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data">P7</td></tr><tr><th scope="row" class="infobox-label"><a href="Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="IA-64" title="IA-64">IA-64</a></td></tr><tr><th scope="row" class="infobox-label">Extensions</th><td class="infobox-data"><div class="plainlist"><ul><li><a href="SpeedStep" title="SpeedStep">EIST</a>, <a href="VT-x" class="mw-redirect" title="VT-x">VT-x</a>, <a href="VT-d" class="mw-redirect" title="VT-d">VT-d</a>, <a href="VT-i" class="mw-redirect" title="VT-i">VT-i</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><div class="plainlist"><ul><li>1, 2, 4 or 8</li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="Random-access_memory" title="Random-access memory">Memory (RAM)</a></th><td class="infobox-data"><div class="plainlist"><ul><li>Up to 1.5 TB</li><li>Up to <a href="DDR3_SDRAM" title="DDR3 SDRAM">DDR3</a> with <a href="Error_correction_code" title="Error correction code">ECC</a> support</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Packages</th><td class="infobox-data"><div class="plainlist"><ul><li>Pin Array Cartridge (PAC)</li><li><a href="Flip-chip" class="mw-redirect" title="Flip-chip">Flip-chip</a> <a href="Land_grid_array" title="Land grid array">land grid array</a> (FC-LGA)</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Sockets</th><td class="infobox-data"><div class="plainlist"><ul><li><a href="PAC_418" class="mw-redirect" title="PAC 418">PAC 418</a></li><li><a href="PAC_611" class="mw-redirect" title="PAC 611">PAC 611</a></li><li><a href="LGA_1248" title="LGA 1248">LGA 1248</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Core names</th><td class="infobox-data"><div class="plainlist"><ul><li>Merced</li><li>McKinley</li><li>Madison 3M/6M/9M</li><li>Deerfield (Madison LV)</li><li>Hondo<a href="#cite_note-7">[b]</a></li><li>Fanwood (Madison DP)</li><li>Montecito</li><li>Montvale</li><li>Tukwila</li><li>Poulson</li><li>Kittison</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Models</th><td class="infobox-data"><div class="plainlist"><ul><li>Itanium</li><li>Itanium 2</li><li>Itanium 9000 series</li><li>Itanium 9100 series</li><li>Itanium 9300 series</li><li>Itanium 9500 series</li><li>Itanium 9700 series</li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Support status</th></tr><tr><td colspan="2" class="infobox-full-data">Unsupported</td></tr></tbody></table>

Itanium (/aɪˈteɪniəm/; eye-TAY-nee-əm) is a discontinued family of <a href="64-bit_computing" title="64-bit computing">64-bit</a> <a href="Intel" title="Intel">Intel</a> <a href="Microprocessor" title="Microprocessor">microprocessors</a> that implement the <a href="Intel_Itanium_architecture" class="mw-redirect" title="Intel Itanium architecture">Intel Itanium architecture</a> (formerly called IA-64). The Itanium architecture originated at <a href="Hewlett-Packard" title="Hewlett-Packard">Hewlett-Packard</a> (HP), and was later jointly developed by HP and Intel. Launching in June 2001, Intel initially marketed the processors for <a href="Enterprise_server" class="mw-redirect" title="Enterprise server">enterprise servers</a> and <a href="High-performance_computing" title="High-performance computing">high-performance computing</a> systems. In the concept phase, engineers said "we could run circles around PowerPC...we could kill the x86". Early predictions were that IA-64 would expand to the lower-end servers, supplanting <a href="Xeon" title="Xeon">Xeon</a>, and eventually penetrate into the <a href="Personal_computer" title="Personal computer">personal computers</a>, eventually to supplant <a href="Reduced_instruction_set_computer" title="Reduced instruction set computer">reduced instruction set computing</a> (RISC) and <a href="Complex_instruction_set_computing" class="mw-redirect" title="Complex instruction set computing">complex instruction set computing</a> (CISC) architectures for all general-purpose applications.

When first released in 2001 after a decade of development, Itanium's performance was disappointing compared to better-established RISC and CISC processors. Emulation to run existing x86 applications and operating systems was particularly poor. Itanium-based systems were produced by HP and its successor <a href="Hewlett_Packard_Enterprise" title="Hewlett Packard Enterprise">Hewlett Packard Enterprise</a> (HPE) as the <a href="HPE_Integrity_Servers" title="HPE Integrity Servers">Integrity Servers</a> line, and by several other manufacturers. In 2008, Itanium was the fourth-most deployed microprocessor architecture for <a href="Enterprise_information_system" title="Enterprise information system">enterprise-class systems</a>, behind <a href="X86-64" title="X86-64">x86-64</a>, <a href="Power_ISA" title="Power ISA">Power ISA</a>, and <a href="SPARC" title="SPARC">SPARC</a>.<a href="#cite_note-ITJungle-8">[6]</a>

In February 2017, Intel released the final generation, Kittson, to test customers, and in May began shipping in volume.<a href="#cite_note-Davis_2017-9">[7]</a><a href="#cite_note-IA-PCWorld-10">[8]</a> It was only used in mission-critical servers from HPE.

In 2019, Intel announced that new orders for Itanium would be accepted until January 30, 2020, and shipments would cease by July 29, 2021.<a href="#cite_note-theend-1">[1]</a> This took place on schedule.<a href="#cite_note-EoL-11">[9]</a>

Itanium never sold well outside enterprise servers and high-performance computing systems, and the architecture was ultimately supplanted by competitor AMD's <a href="X86-64" title="X86-64">x86-64</a> (also called AMD64) architecture. x86-64 is a compatible extension to the 32-bit x86 architecture, implemented by, for example, Intel's own Xeon line and <a href="Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">AMD</a>'s <a href="Opteron" title="Opteron">Opteron</a> line. By 2009, most servers were being shipped with x86-64 processors, and they dominate the low cost desktop and laptop markets which were not initially targeted by Itanium.<a href="#cite_note-Gartner_2009-q4-12">[10]</a> In an article titled "Intel's Itanium is finally dead: The Itanic sunken by the x86 juggernaut" Techspot declared "Itanium's promise ended up sunken by a lack of legacy 32-bit support and difficulties in working with the architecture for writing and maintaining software", while the dream of a single dominant <a href="Instruction_set_architecture" title="Instruction set architecture">ISA</a> would be realized by the AMD64 extensions.<a href="#cite_note-13">[11]</a>

<div class="mw-heading mw-heading2"><h2 id="History">History</h2></div>

<div class="mw-heading mw-heading3"><h3 id="Development:_1989–2001">Development: 1989–2001</h3></div>

<div class="mw-heading mw-heading4"><h4 id="Inception:_1989–1994">Inception: 1989–1994</h4></div>

In 1989, HP started to research an architecture that would exceed the expected limits of the <a href="Reduced_instruction_set_computer" title="Reduced instruction set computer">reduced instruction set computer</a> (RISC) architectures caused by the great increase in complexity needed for executing multiple <a href="Instructions_per_cycle" title="Instructions per cycle">instructions per cycle</a> due to the need for dynamic <a href="Data_dependency" title="Data dependency">dependency</a> checking and precise <a href="Exception_handling" title="Exception handling">exception handling</a>.<a href="#cite_note-16">[c]</a> HP hired <a href="Bob_Rau" title="Bob Rau">Bob Rau</a> of <a href="Cydrome" title="Cydrome">Cydrome</a> and <a href="Josh_Fisher" title="Josh Fisher">Josh Fisher</a> of <a href="Multiflow" title="Multiflow">Multiflow</a>, the pioneers of <a href="Very_long_instruction_word" title="Very long instruction word">very long instruction word</a> (VLIW) computing. One VLIW instruction word can contain several independent <a href="Instruction_(computer_science)" class="mw-redirect" title="Instruction (computer science)">instructions</a>, which can be executed in parallel without having to evaluate them for independence. A <a href="Compiler" title="Compiler">compiler</a> must attempt to find <a href="Instruction-level_parallelism" title="Instruction-level parallelism">valid combinations of instructions that can be executed at the same time</a>, effectively performing the instruction scheduling that conventional <a href="Superscalar_processor" title="Superscalar processor">superscalar processors</a> must do in hardware at runtime.

HP researchers modified the classic VLIW into a new type of architecture, later named <a href="Explicitly_Parallel_Instruction_Computing" class="mw-redirect" title="Explicitly Parallel Instruction Computing">Explicitly Parallel Instruction Computing</a> (EPIC), which differs by: having template bits which show which instructions are independent inside and between the bundles of three instructions, which enables the explicitly parallel execution of multiple bundles and increasing the processors' <a href="Wide-issue" title="Wide-issue">issue width</a> without the need to recompile; by <a href="Predication_(computer_architecture)" title="Predication (computer architecture)">predication</a> of instructions to reduce the need for <a href="Branch_(computer_science)" title="Branch (computer science)">branches</a>; and by full interlocking to eliminate the <a href="Delay_slot" title="Delay slot">delay slots</a>. In EPIC the assignment of <a href="Execution_unit" title="Execution unit">execution units</a> to instructions and the timing of their issuing can be decided by hardware, unlike in the classic VLIW. HP intended to use these features in PA-WideWord, the planned successor to their <a href="PA-RISC" title="PA-RISC">PA-RISC</a> ISA. EPIC was intended to provide the best balance between the efficient use of silicon area and electricity, and general-purpose flexibility.<a href="#cite_note-Understanding_EPIC-15">[13]</a><a href="#cite_note-HP_Labs-17">[14]</a> In 1993 HP held an internal competition to design the best (simulated) microarchitectures of a RISC and an EPIC type, led by Jerry Huck and <a href="Rajiv_Gupta_(technocrat)" title="Rajiv Gupta (technocrat)">Rajiv Gupta</a> respectively. The EPIC team won, with over double the simulated performance of the RISC competitor.<a href="#cite_note-nyt_merced-18">[15]</a>

At the same time Intel was also looking for ways to make better ISAs. In 1989 Intel had launched the <a href="Intel_i860" title="Intel i860">i860</a>, which it marketed for workstations, servers, and <a href="Intel_iPSC#iPSC/860" title="Intel iPSC">iPSC</a> and <a href="Intel_Paragon" title="Intel Paragon">Paragon</a> supercomputers. It differed from other RISCs by being able to switch between the normal single instruction per cycle mode, and a mode where pairs of instructions are explicitly defined as parallel so as to execute them in the same cycle without having to do dependency checking. Another distinguishing feature were the instructions for an exposed floating-point pipeline, that enabled the tripling of throughput compared to the conventional floating-point instructions. Both of these features were left largely unused because compilers didn't support them, a problem that later challenged Itanium too. Without them, i860's parallelism (and thus performance) was no better than other RISCs, so it failed in the market. Itanium would adopt a more flexible form of explicit parallelism than i860 had.<a href="#cite_note-19">[16]</a>

In November 1993 HP approached Intel, seeking collaboration on an innovative future architecture.<a href="#cite_note-countdown-20">[17]</a><a href="#cite_note-22">[19]</a> At the time Intel was looking to extend x86 to 64 bits in a processor codenamed P7, which they found challenging.<a href="#cite_note-23">[20]</a> Later Intel claimed that four different design teams had explored 64-bit extensions, but each of them concluded that it was not economically feasible.<a href="#cite_note-24">[21]</a> At the meeting with HP, Intel's engineers were impressed when Jerry Huck and <a href="Rajiv_Gupta_(technocrat)" title="Rajiv Gupta (technocrat)">Rajiv Gupta</a> presented the PA-WideWord architecture they had designed to replace <a href="PA-RISC" title="PA-RISC">PA-RISC</a>. "When we saw WideWord, we saw a lot of things we had only been looking at doing, already in their full glory", said Intel's <a href="John_Crawford_(engineer)" title="John Crawford (engineer)">John Crawford</a>, who in 1994 became the chief architect of Merced, and who had earlier argued against extending the x86 with P7. HP's Gupta recalled: "I looked Albert Yu [Intel's general manager for microprocessors] in the eyes and showed him we could run circles around <a href="PowerPC" title="PowerPC">PowerPC</a>, that we could kill PowerPC, that we could kill the x86."<a href="#cite_note-gambles-25">[22]</a> Soon Intel and HP started conducting in-depth technical discussions at an HP office, where each side had six<a href="#cite_note-28">[25]</a> engineers who exchanged and discussed both companies' confidential architectural research. They then decided to use not only PA-WideWord, but also the more experimental <a href="HP_Labs" title="HP Labs">HP Labs</a> PlayDoh as the source of their joint future architecture.<a href="#cite_note-simplicity-14">[12]</a><a href="#cite_note-29">[26]</a> Convinced of the superiority of the new project, in 1994 Intel canceled their existing plans for P7.

In June 1994 Intel and HP announced their joint effort to make a new ISA that would adopt ideas of Wide Word and VLIW. Yu declared: "If I were competitors, I'd be really worried. If you think you have a future, you don't."<a href="#cite_note-gambles-25">[22]</a> On P7's future, Intel said the alliance would impact it, but "it is not clear" whether it would "fully encompass the new architecture".<a href="#cite_note-30">[27]</a><a href="#cite_note-31">[28]</a>

Later the same month, Intel said that some of the first features of the new architecture would start appearing on Intel chips as early as the P7, but the full version would appear sometime later.<a href="#cite_note-32">[29]</a>

In August 1994 <a href="EE_Times" title="EE Times">EE Times</a> reported that Intel told investors that P7 was being re-evaluated and possibly canceled in favor of the HP processor. Intel immediately issued a clarification, saying that P7 is still being defined, and that HP may contribute to its architecture. Later it was confirmed that the P7 codename had indeed passed to the HP-Intel processor. By early 1996 Intel revealed its new codename, Merced.<a href="#cite_note-33">[30]</a><a href="#cite_note-34">[31]</a>

HP believed that it was no longer cost-effective for individual enterprise systems companies such as itself to develop proprietary microprocessors, so it partnered with Intel in 1994 to develop the IA-64 architecture, derived from EPIC. Intel was willing to undertake the very large development effort on IA-64 in the expectation that the resulting microprocessor would be used by the majority of enterprise systems manufacturers. HP and Intel initiated a large joint development effort with a goal of delivering the first product, Merced, in 1998.<a href="#cite_note-HP_Labs-17">[14]</a>

<div class="mw-heading mw-heading4"><h4 id="Design_and_delays:_1994–2001">Design and delays: 1994–2001</h4></div>

Merced was designed by a team of 500, which Intel later admitted was too inexperienced, with many recent college graduates. Crawford (Intel) was the chief architect, while Huck (HP) held the second position. Early in the development HP and Intel had a disagreement where Intel wanted more dedicated hardware for more floating-point instructions. HP prevailed upon the discovery of <a href="Pentium_FDIV_bug" title="Pentium FDIV bug">a floating-point hardware bug</a> in Intel's <a href="Pentium_(original)" title="Pentium (original)">Pentium</a>. When Merced was <a href="Floorplan_(microelectronics)" title="Floorplan (microelectronics)">floorplanned</a> for the first time in mid-1996, it turned out to be far too large, "this was a lot worse than anything I'd seen before", said Crawford. The designers had to reduce the complexity (and thus performance) of subsystems, including the x86 unit and cutting the L2 cache to 96 KB.<a href="#cite_note-35">[d]</a> Eventually it was agreed that the size target could only be reached by using the <a href="180_nm" class="mw-redirect" title="180 nm">180 nm</a> process instead of the intended <a href="250_nm_process" title="250 nm process">250 nm</a>. Later problems emerged with attempts to speed up the critical paths without disturbing the other circuits' speed. Merced was <a href="Tape-out" title="Tape-out">taped out</a> on 4 July 1999, and in August Intel produced the first complete test chip.<a href="#cite_note-gambles-25">[22]</a>

The expectations for Merced waned over time as delays and performance deficiencies emerged, shifting the focus and onus for success onto the HP-led second Itanium design, codenamed McKinley. In July 1997 the switch to the <a href="180_nm_process" title="180 nm process">180 nm process</a> delayed Merced into the second half of 1999.<a href="#cite_note-36">[32]</a> Shortly before the reveal of <a href="Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a> at the Microprocessor Forum in October 1997, an analyst of the <a href="Microprocessor_Report" title="Microprocessor Report">Microprocessor Report</a> said that Itanium would "not show the competitive performance until 2001. It will take the second version of the chip for the performance to get shown".<a href="#cite_note-37">[33]</a> At the Forum, Intel's <a href="Fred_Pollack" title="Fred Pollack">Fred Pollack</a> originated the "wait for McKinley" mantra when he said that it would double the Merced's performance and would "knock your socks off",<a href="#cite_note-cnet_unveil_epic-38">[34]</a><a href="#cite_note-39">[35]</a> while using the same 180 nm process as Merced.<a href="#cite_note-40">[36]</a> Pollack also said that Merced's x86 performance would be lower than the fastest x86 processors, and that x86 would "continue to grow at its historical rates".<a href="#cite_note-cnet_unveil_epic-38">[34]</a> Intel said that IA-64 won't have much presence in the consumer market for 5 to 10 years.<a href="#cite_note-41">[37]</a>

Later it was reported that HP's motivation when starting to design McKinley in 1996 was to have more control over the project so as to avoid the issues affecting Merced's performance and schedule.<a href="#cite_note-zdnet_wait-42">[38]</a><a href="#cite_note-43">[39]</a> The design team finalized McKinley's project goals in 1997.<a href="#cite_note-HP_McKinley_wp-44">[40]</a> In late May 1998 Merced was delayed to mid-2000, and by August 1998 analysts were questioning its commercial viability, given that McKinley would arrive shortly after with double the performance, as delays were causing Merced to turn into simply a development vehicle for the Itanium ecosystem. The "wait for McKinley" narrative was becoming prevalent.<a href="#cite_note-45">[41]</a> The same day it was reported that due to the delays, HP would extend its line of PA-RISC <a href="PA-8000" title="PA-8000">PA-8000</a> series processors from PA-8500 to as far as PA-8900.<a href="#cite_note-46">[42]</a> In October 1998 HP announced its plans for four more generations of PA-RISC processors, with PA-8900 set to reach 1.2 GHz in 2003.<a href="#cite_note-47">[43]</a>

By March 1999 some analysts expected Merced to ship in volume only in 2001, but the volume was widely expected to be low as most customers would wait for McKinley.<a href="#cite_note-zdnet_wait-42">[38]</a> In May 1999, two months before Merced's <a href="Tape-out" title="Tape-out">tape-out</a>, an analyst said that failure to tape-out before July would result in another delay.<a href="#cite_note-48">[44]</a> In July 1999, upon reports that the first silicon would be made in late August, analysts predicted a delay to late 2000, and came into agreement that Merced would be used chiefly for debugging and testing the IA-64 software. Linley Gwennap of <a href="Microprocessor_Report" title="Microprocessor Report">MPR</a> said of Merced that "at this point, everyone is expecting it's going to be late and slow, and the real advance is going to come from McKinley. What this does is puts a lot more pressure on McKinley and for that team to deliver".<a href="#cite_note-may_slip-49">[45]</a> By then, Intel had revealed that Merced would be initially priced at $5000.<a href="#cite_note-50">[46]</a> In August 1999 HP advised some of their customers to skip Merced and wait for McKinley.<a href="#cite_note-51">[47]</a> By July 2000 HP told the press that the first Itanium systems would be for niche uses, and that "You're not going to put this stuff near your data center for several years."; HP expected its Itanium systems to outsell the PA-RISC systems only in 2005.<a href="#cite_note-52">[48]</a> The same July Intel told of another delay, due to a <a href="Stepping_level" title="Stepping level">stepping</a> change to fix bugs. Now only "pilot systems" would ship that year, while the general availability was pushed to the "first half of 2001". Server makers had largely forgone spending on the R&D for the Merced-based systems, instead using motherboards or whole servers of Intel's design. To foster a wide ecosystem, by mid-2000 Intel had provided 15,000 Itaniums in 5,000 systems to software developers and hardware designers.<a href="#cite_note-53">[49]</a> In March 2001 Intel said Itanium systems would begin shipping to customers in the second quarter, followed by a broader deployment in the second half of the year. By then even Intel publicly acknowledged that many customers would wait for McKinley.<a href="#cite_note-54">[50]</a>

<div class="mw-heading mw-heading4"><h4 id="Expectations">Expectations</h4></div>

During development, Intel, HP, and industry analysts predicted that IA-64 would dominate first in 64-bit servers and workstations, then expand to the lower-end servers, supplanting Xeon, and finally penetrate into the <a href="Personal_computer" title="Personal computer">personal computers</a>, eventually to supplant RISC and <a href="Complex_instruction_set_computing" class="mw-redirect" title="Complex instruction set computing">complex instruction set computing</a> (CISC) architectures for all general-purpose applications, though not replacing x86 "for the foreseeable future" according to Intel.<a href="#cite_note-57">[53]</a><a href="#cite_note-nyt_merced-18">[15]</a><a href="#cite_note-58">[54]</a><a href="#cite_note-59">[55]</a><a href="#cite_note-anand-60">[56]</a><a href="#cite_note-Venturebeat-61">[57]</a> In 1997-1998, Intel CEO <a href="Andy_Grove" class="mw-redirect" title="Andy Grove">Andy Grove</a> predicted that Itanium would not come to the desktop computers for four of five years after launch, and said "I don't see Merced appearing on a mainstream desktop inside of a decade".<a href="#cite_note-62">[58]</a><a href="#cite_note-nyt_merced-18">[15]</a> In contrast, Itanium was expected to capture 70% of the 64-bit server market in 2002.<a href="#cite_note-63">[59]</a> Already in 1998 Itanium's focus on the high end of the computer market was criticized for making it vulnerable to challengers expanding from the lower-end market segments, but many people in the computer industry feared voicing doubts about Itanium in the fear of Intel's retaliation.<a href="#cite_note-nyt_merced-18">[15]</a>

<a href="Compaq" title="Compaq">Compaq</a> and <a href="Silicon_Graphics" title="Silicon Graphics">Silicon Graphics</a> decided to abandon further development of the <a href="DEC_Alpha" title="DEC Alpha">Alpha</a> and <a href="MIPS_architecture" title="MIPS architecture">MIPS</a> architectures respectively in favor of migrating to IA-64.<a href="#cite_note-cautionary-64">[60]</a>

Several groups ported operating systems for the architecture, including <a href="Microsoft_Windows" title="Microsoft Windows">Microsoft Windows</a>, <a href="OpenVMS" title="OpenVMS">OpenVMS</a>, <a href="Linux" title="Linux">Linux</a>, <a href="HP-UX" title="HP-UX">HP-UX</a>, <a href="Solaris_(operating_system)" class="mw-redirect" title="Solaris (operating system)">Solaris</a>,<a href="#cite_note-Solaris-Merced1-65">[61]</a><a href="#cite_note-Solaris-Merced2-66">[62]</a><a href="#cite_note-Solaris-Merced3-67">[63]</a>

<a href="Tru64_UNIX" title="Tru64 UNIX">Tru64 UNIX</a>,<a href="#cite_note-cautionary-64">[60]</a> and <a href="Project_Monterey" title="Project Monterey">Monterey/64</a>.<a href="#cite_note-68">[64]</a>

The latter three were canceled before reaching the market. By 1997, it was apparent that the IA-64 architecture and the compiler were much more difficult to implement than originally thought, and the delivery timeframe of Merced began slipping.<a href="#cite_note-may_slip-49">[45]</a>

Intel announced the official name of the processor, Itanium, on October 4, 1999.<a href="#cite_note-69">[65]</a>

Within hours, the name Itanic had been coined on a <a href="Usenet" title="Usenet">Usenet</a> newsgroup, a reference to the <a href="RMS_Titanic" class="mw-redirect" title="RMS Titanic">RMS Titanic</a>, the "unsinkable" <a href="Ocean_liner" title="Ocean liner">ocean liner</a> that sank on her maiden voyage in 1912.<a href="#cite_note-70">[66]</a> "Itanic" was then used often by <a href="The_Register" title="The Register">The Register</a>,<a href="#cite_note-Reg_Itanic-71">[67]</a> and others,<a href="#cite_note-72">[68]</a><a href="#cite_note-73">[69]</a><a href="#cite_note-74">[70]</a> to imply that the multibillion-dollar investment in Itanium—and the early hype associated with it—would be followed by its relatively quick demise.

<div class="mw-heading mw-heading3"><h3 id="Itanium_(Merced):_2001">Itanium (Merced): 2001</h3></div>

<table class="infobox"><caption class="infobox-title">Itanium (Merced)</caption><tbody><tr><td colspan="2" class="infobox-image"><div class="infobox-caption">Itanium processor</div></td></tr><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">29 May–June 2001</td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">10 April 2003<a href="#cite_note-75">[71]</a></td></tr><tr><th scope="row" class="infobox-label">Common manufacturer</th><td class="infobox-data"><div class="plainlist"><ul><li>Intel</li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="Central_processing_unit" title="Central processing unit">CPU</a> <a href="Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">733  to 800 MHz</td></tr><tr><th scope="row" class="infobox-label"><a href="Front-side_bus" title="Front-side bus">FSB</a> speeds</th><td class="infobox-data">266 MT/s</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">96 KB</td></tr><tr><th scope="row" class="infobox-label">L3 cache</th><td class="infobox-data">2 or 4 MB</td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><div class="plainlist"><ul><li>1</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Socket</th><td class="infobox-data"><div class="plainlist"><ul><li><a href="PAC418" title="PAC418">PAC418</a></li></ul></div></td></tr></tbody></table>

After having sampled 40,000 chips to the partners, Intel launched Itanium on May 29, 2001, with first OEM systems from HP, IBM and Dell shipping to customers in June.<a href="#cite_note-76">[72]</a><a href="#cite_note-77">[73]</a> By then Itanium's performance was not superior to competing RISC and CISC processors.<a href="#cite_note-78">[74]</a>

Itanium competed at the low-end (primarily four-<a href="Central_processing_unit" title="Central processing unit">CPU</a> and smaller systems) with servers based on <a href="X86" title="X86">x86</a> processors, and at the high-end with <a href="IBM_Power_microprocessors" title="IBM Power microprocessors">IBM POWER</a> and <a href="Sun_Microsystems" title="Sun Microsystems">Sun Microsystems</a> <a href="SPARC" title="SPARC">SPARC</a> processors. Intel repositioned Itanium to focus on the high-end business and <a href="High-performance_computing" title="High-performance computing">HPC</a> computing markets, attempting to duplicate the x86's successful "horizontal" market (i.e., single architecture, multiple systems vendors). The success of this initial processor version was limited to replacing the <a href="PA-RISC" title="PA-RISC">PA-RISC</a> in HP systems, <a href="DEC_Alpha" title="DEC Alpha">Alpha</a> in Compaq systems and <a href="MIPS_architecture" title="MIPS architecture">MIPS</a> in <a href="Silicon_Graphics" title="Silicon Graphics">SGI</a> systems, though IBM also delivered a supercomputer based on this processor.<a href="#cite_note-Thunder-79">[75]</a>

POWER and SPARC remained strong, while the <a href="32-bit_computing" title="32-bit computing">32-bit</a> x86 architecture continued to grow into the enterprise space, building on the economies of scale fueled by its enormous installed base.

Only a few thousand systems using the original Merced Itanium processor were sold, due to relatively poor performance, high cost and limited software availability.<a href="#cite_note-80">[76]</a> Recognizing that the lack of software could be a serious problem for the future, Intel made thousands of these early systems available to independent software vendors (ISVs) to stimulate development. HP and Intel brought the next-generation Itanium 2 processor to the market a year later. Few of the microarchitectural features of Merced would be carried over to all the subsequent Itanium designs, including the 16+16 KB L1 cache size and the 6-wide (two-bundle) instruction decoding.

<div class="mw-heading mw-heading3"><h3 id="Itanium_2_(McKinley_and_Madison):_2002–2006">Itanium 2 (McKinley and Madison): 2002–2006</h3></div>

<table class="infobox"><caption class="infobox-title">Itanium 2 (McKinley and Madison)</caption><tbody><tr><td colspan="2" class="infobox-image"><div class="infobox-caption">Itanium 2 processor</div></td></tr><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">8 July 2002</td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">16 November 2007<a href="#cite_note-84">[80]</a></td></tr><tr><th scope="row" class="infobox-label">Designed by</th><td class="infobox-data"><a href="Hewlett-Packard" title="Hewlett-Packard">HP</a> and Intel</td></tr><tr><th scope="row" class="infobox-label">Product code</th><td class="infobox-data">McKinley, Madison, Deerfield, Madison 9M, Fanwood</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="Central_processing_unit" title="Central processing unit">CPU</a> <a href="Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">900  to 1667 MHz</td></tr><tr><th scope="row" class="infobox-label"><a href="Front-side_bus" title="Front-side bus">FSB</a> speeds</th><td class="infobox-data">400  to 667 MT/s</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">256 KB</td></tr><tr><th scope="row" class="infobox-label">L3 cache</th><td class="infobox-data">1.5–9 MB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data"><a href="180_nm" class="mw-redirect" title="180 nm">180 nm</a> to <a href="130_nm" class="mw-redirect" title="130 nm">130 nm</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><div class="plainlist"><ul><li>1</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Socket</th><td class="infobox-data"><div class="plainlist"><ul><li><a href="PAC611" title="PAC611">PAC611</a></li></ul></div></td></tr></tbody></table>

The Itanium 2 processor was released in July 2002, and was marketed for enterprise servers rather than for the whole gamut of high-end computing. The first Itanium 2, code-named McKinley, was jointly developed by HP and Intel, led by the HP team at <a href="Fort_Collins%2C_Colorado" title="Fort Collins, Colorado">Fort Collins, Colorado</a>, <a href="Tape-out" title="Tape-out">taping out</a> in December 2000. It relieved many of the performance problems of the original Itanium processor, which were mostly caused by an inefficient memory subsystem by approximately halving the latency and doubling the fill bandwidth of each of the three levels of cache, while expanding the L2 cache from 96 to 256 KB. Floating-point data is excluded from the L1 cache, because the L2 cache's higher bandwidth is more beneficial to typical floating-point applications than low latency. The L3 cache is now integrated on-chip rather than on a separate die, tripling in associativity and doubling in bus width. McKinley also greatly increases the number of possible instruction combinations in a VLIW-bundle and reaches 25% higher frequency, despite having only eight pipeline stages versus Merced's ten.<a href="#cite_note-85">[81]</a><a href="#cite_note-HP_McKinley_wp-44">[40]</a>

McKinley contains 221 million transistors (of which 25 million are for logic and 181 million for L3 cache), measured 19.5 mm by 21.6 mm (421 mm2) and was fabricated in a 180 nm, bulk CMOS process with six layers of aluminium metallization.<a href="#cite_note-86">[82]</a><a href="#cite_note-87">[83]</a><a href="#cite_note-88">[84]</a> In May 2003 it was disclosed that some McKinley processors can suffer from a critical-path erratum leading to a system's crashing. It can be avoided by lowering the processor frequency to 800 MHz.<a href="#cite_note-89">[85]</a>

In 2003, <a href="Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">AMD</a> released the <a href="Opteron" title="Opteron">Opteron</a> CPU, which implements its own <a href="64-bit_computing" title="64-bit computing">64-bit</a> architecture called <a href="AMD64" class="mw-redirect" title="AMD64">AMD64</a>. The Opteron gained rapid acceptance in the enterprise server space because it provided an easy upgrade from <a href="X86" title="X86">x86</a>. Under the influence of Microsoft, Intel responded by implementing AMD's x86-64 <a href="Instruction_set_architecture" title="Instruction set architecture">instruction set architecture</a> instead of IA-64 in its <a href="Xeon" title="Xeon">Xeon</a> microprocessors in 2004, resulting in a new industry-wide de facto standard.<a href="#cite_note-cautionary-64">[60]</a>

In 2003, Intel released a new Itanium 2 family member, codenamed Madison, initially with up to 1.5 GHz frequency and 6 MB of L3 cache. The Madison 9M chip released in November 2004 had 9 MB of L3 cache and frequency up to 1.6 GHz, reaching 1.67 GHz in July 2005. Both chips used a 130 nm process and were the basis of all new Itanium processors until Montecito was released in July 2006, specifically Deerfield being a low wattage Madison, and Fanwood being a version of Madison 9M for lower-end servers with one or two CPU sockets.

In November 2005, the major Itanium server manufacturers joined with Intel and a number of software vendors to form the Itanium Solutions Alliance to promote the architecture and accelerate the software porting effort.<a href="#cite_note-ISA-90">[86]</a>

The Alliance announced that its members would invest $10 billion in the Itanium Solutions Alliance by the end of the decade.<a href="#cite_note-91">[87]</a>

<div class="mw-heading mw-heading3"><h3 id="Itanium_2_9000_and_Itanium_9100:_2006_and_2007">Itanium 2 9000 and Itanium 9100: 2006 and 2007</h3></div>

<table class="infobox"><caption class="infobox-title">9000 and 9100 series</caption><tbody><tr><td colspan="2" class="infobox-image"><div class="infobox-caption">Intel Itanium 2 9000 (<a href="Heat_spreader" title="Heat spreader">heat spreader</a> <a href="Decapping" title="Decapping">removed</a>)</div></td></tr><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">18 July 2006</td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">26 August 2011<a href="#cite_note-92">[88]</a></td></tr><tr><th scope="row" class="infobox-label">Product code</th><td class="infobox-data">Montecito, Montvale</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="Central_processing_unit" title="Central processing unit">CPU</a> <a href="Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">1.4 GHz to 1.67 GHz</td></tr><tr><th scope="row" class="infobox-label"><a href="Front-side_bus" title="Front-side bus">FSB</a> speeds</th><td class="infobox-data">400  to 667 MT/s</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">256 KB (D) + 1 MB (I)</td></tr><tr><th scope="row" class="infobox-label">L3 cache</th><td class="infobox-data">6–24 MB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data"><a href="90_nm" class="mw-redirect" title="90 nm">90 nm</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><div class="plainlist"><ul><li>1 or 2</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Socket</th><td class="infobox-data"><div class="plainlist"><ul><li><a href="PAC611" title="PAC611">PAC611</a></li></ul></div></td></tr></tbody></table>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Montecito_(processor)" title="Montecito (processor)">Montecito (processor)</a></div>

In early 2003, due to the success of IBM's dual-core <a href="POWER4" title="POWER4">POWER4</a>, Intel announced that the first <a href="90_nm" class="mw-redirect" title="90 nm">90 nm</a> Itanium processor, codenamed Montecito, would be delayed to 2005 so as to change it into a dual-core, thus merging it with the Chivano project.<a href="#cite_note-93">[89]</a><a href="#cite_note-qa-94">[90]</a> In September 2004 Intel demonstrated a working Montecito system, and claimed that the inclusion of <a href="Hyper-threading" title="Hyper-threading">hyper-threading</a> increases Montecito's performance by 10-20% and that its frequency could reach 2 GHz.<a href="#cite_note-monty-95">[91]</a><a href="#cite_note-96">[92]</a> After a delay to "mid-2006" and reduction of the frequency to 1.6 GHz,<a href="#cite_note-97">[93]</a> on July 18 Intel delivered Montecito (marketed as the Itanium 2 9000 series), a <a href="Multi-core_processor" title="Multi-core processor">dual-core</a> processor with a <a href="Multithreading_(computer_architecture)#Coarse-grained_multithreading" title="Multithreading (computer architecture)">switch-on-event multithreading</a> and split 256 KB + 1 MB L2 caches that roughly doubled the performance and decreased the energy consumption by about 20 percent.<a href="#cite_note-CW1-98">[94]</a> At 596 mm² die size and 1.72 billion transistors it was the largest microprocessor at the time. It was supposed to feature <a href="Foxton_Technology" title="Foxton Technology">Foxton Technology</a>, a very sophisticated frequency regulator, which failed to pass validation and was thus not enabled for customers.

Intel released the Itanium 9100 series, codenamed Montvale, in November 2007, retiring the "Itanium 2" brand.<a href="#cite_note-IW1-99">[95]</a> Originally intended to use the <a href="65_nm_process" title="65 nm process">65 nm process</a>,<a href="#cite_note-idf04f-100">[96]</a> it was changed into a fix of Montecito, enabling the demand-based switching (like <a href="EIST" class="mw-redirect" title="EIST">EIST</a>) and up to 667 MT/s <a href="Front-side_bus" title="Front-side bus">front-side bus</a>, which were intended for Montecito, plus a core-level <a href="Lockstep_(computing)" title="Lockstep (computing)">lockstep</a>.<a href="#cite_note-monty-95">[91]</a> Montecito and Montvale were the last Itanium processors in which design <a href="Hewlett-Packard" title="Hewlett-Packard">Hewlett-Packard</a>'s engineering team at Fort Collins had a key role, as the team was subsequently transferred to Intel's ownership.<a href="#cite_note-101">[97]</a>

<div class="mw-heading mw-heading3"><h3 id="Itanium_9300_(Tukwila):_2010">Itanium 9300 (Tukwila): 2010</h3></div>

<table class="infobox"><caption class="infobox-title">9300 series</caption><tbody><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">8 February 2010</td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">2nd quarter of 2014</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="Central_processing_unit" title="Central processing unit">CPU</a> <a href="Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">1.33  to 1.73 GHz</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">256 KB (D) + 512 KB (I)</td></tr><tr><th scope="row" class="infobox-label">L3 cache</th><td class="infobox-data">10–24 MB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data"><a href="65_nm" class="mw-redirect" title="65 nm">65 nm</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><div class="plainlist"><ul><li>2 or 4</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Socket</th><td class="infobox-data"><div class="plainlist"><ul><li>FC-LGA6 (<a href="LGA1248" class="mw-redirect" title="LGA1248">LGA1248</a>)</li></ul></div></td></tr></tbody></table>

<table class="infobox"><caption class="infobox-title">9500 and 9700 series</caption><tbody><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">8 November 2012</td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">30 January 2020<a href="#cite_note-102">[98]</a></td></tr><tr><th scope="row" class="infobox-label">Product code</th><td class="infobox-data">Poulson, Kittson</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="Central_processing_unit" title="Central processing unit">CPU</a> <a href="Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">1.73  to 2.67 GHz</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">256 KB (D) + 512 KB (I)</td></tr><tr><th scope="row" class="infobox-label">L3 cache</th><td class="infobox-data">20–32 MB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data"><a href="32_nm" class="mw-redirect" title="32 nm">32 nm</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><div class="plainlist"><ul><li>4 or 8</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Socket</th><td class="infobox-data"><div class="plainlist"><ul><li>FC-LGA6 (<a href="LGA1248" class="mw-redirect" title="LGA1248">LGA1248</a>)</li></ul></div></td></tr></tbody></table>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Tukwila_(processor)" title="Tukwila (processor)">Tukwila (processor)</a></div>

The original code name for the first Itanium with more than two cores was Tanglewood, but it was changed to Tukwila in late 2003 due to trademark issues.<a href="#cite_note-103">[99]</a><a href="#cite_note-104">[100]</a> Intel discussed a "middle-of-the-decade Itanium" to succeed Montecito, achieving ten times the performance of Madison.<a href="#cite_note-105">[101]</a><a href="#cite_note-qa-94">[90]</a> It was being designed by the famed <a href="DEC_Alpha" title="DEC Alpha">DEC Alpha</a> team and was expected have eight new multithreading-focused cores. Intel claimed "a lot more than two" cores and more than seven times the performance of Madison.<a href="#cite_note-106">[102]</a><a href="#cite_note-107">[103]</a><a href="#cite_note-108">[104]</a> In early 2004 Intel told of "plans to achieve up to double the performance over the Intel Xeon processor family at platform cost parity by 2007".<a href="#cite_note-109">[105]</a> By early 2005 Tukwila was redefined, now having fewer cores but focusing on single-threaded performance and multiprocessor scalability.<a href="#cite_note-110">[106]</a>

In March 2005, Intel disclosed some details of Tukwila, the next Itanium processor after Montvale, to be released in 2007. Tukwila would have <a href="Multi-core_processor" title="Multi-core processor">four processor cores</a> and would replace the Itanium bus with a new <a href="Common_System_Interface" class="mw-redirect" title="Common System Interface">Common System Interface</a>, which would also be used by a new Xeon processor.<a href="#cite_note-CSI-111">[107]</a> Tukwila was to have a "common platform architecture" with a Xeon codenamed Whitefield,<a href="#cite_note-idf04f-100">[96]</a> which was canceled in October 2005,<a href="#cite_note-112">[108]</a> when Intel revised Tukwila's delivery date to late 2008.<a href="#cite_note-zdnet_2005_slip-113">[109]</a> In May 2009, the schedule for Tukwila, was revised again, with the release to OEMs planned for the first quarter of 2010.<a href="#cite_note-INQ09-114">[110]</a>

The Itanium 9300 series processor, codenamed Tukwila, was released on February 8, 2010, with greater performance and memory capacity.<a href="#cite_note-eweek-tukwila-115">[111]</a>

The device uses a 65 nm process, includes two to four cores, up to 24 <a href="Mebibyte" class="mw-redirect" title="Mebibyte">MB</a> on-die caches, <a href="Hyper-Threading" class="mw-redirect" title="Hyper-Threading">Hyper-Threading</a> technology and integrated memory controllers. It implements <a href="ECC_memory" title="ECC memory">double-device data correction</a>, which helps to fix memory errors. Tukwila also implements <a href="Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">Intel QuickPath Interconnect</a> (QPI) to replace the Itanium bus-based architecture. It has a peak interprocessor bandwidth of 96 GB/s and a peak memory bandwidth of 34 GB/s. With QuickPath, the processor has integrated memory controllers and interfaces the memory directly, using QPI interfaces to directly connect to other processors and I/O hubs. QuickPath is also used on Intel <a href="X86-64" title="X86-64">x86-64</a> processors using the <a href="Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a> microarchitecture, which possibly enabled Tukwila and Nehalem to use the same chipsets.<a href="#cite_note-Kittson-116">[112]</a>

Tukwila incorporates two memory controllers, each of which has two links to Scalable Memory Buffers, which in turn support multiple <a href="DDR3_SDRAM" title="DDR3 SDRAM">DDR3</a> <a href="DIMM" title="DIMM">DIMMs</a>,<a href="#cite_note-TukwilaDelay-117">[113]</a>

much like the Nehalem-based Xeon processor code-named <a href="Beckton_(microprocessor)" class="mw-redirect" title="Beckton (microprocessor)">Beckton</a>.<a href="#cite_note-DailyTech_Server-118">[114]</a>

<div class="mw-heading mw-heading3"><h3 id="HP_vs._Oracle">HP vs. Oracle</h3></div>

During the 2012 Hewlett-Packard Co. v. Oracle Corp. support lawsuit, court documents unsealed by a Santa Clara County Court judge revealed that in 2008, Hewlett-Packard had paid Intel around $440 million to keep producing and updating Itanium microprocessors from 2009 to 2014. In 2010, the two companies signed another $250 million deal, which obliged Intel to continue making Itanium CPUs for HP's machines until 2017. Under the terms of the agreements, HP had to pay for chips it gets from Intel, while Intel launches Tukwila, Poulson, Kittson, and Kittson+ chips in a bid to gradually boost performance of the platform.<a href="#cite_note-119">[115]</a><a href="#cite_note-120">[116]</a>

<div class="mw-heading mw-heading3"><h3 id="Itanium_9500_(Poulson):_2012">Itanium 9500 (Poulson): 2012</h3></div>

Intel first mentioned Poulson on March 1, 2005, at the Spring <a href="Intel_Developer_Forum" title="Intel Developer Forum">IDF</a>.<a href="#cite_note-121">[117]</a> In June 2007 Intel said that Poulson would use a <a href="32_nanometer" class="mw-redirect" title="32 nanometer">32 nm</a> process technology, skipping the <a href="45_nanometer" class="mw-redirect" title="45 nanometer">45 nm</a> process.<a href="#cite_note-mercury-122">[118]</a> This was necessary for catching up after Itanium's delays left it at <a href="90_nm" class="mw-redirect" title="90 nm">90 nm</a> competing against <a href="65_nm" class="mw-redirect" title="65 nm">65 nm</a> and <a href="45_nm" class="mw-redirect" title="45 nm">45 nm</a> processors.

At <a href="International_Solid-State_Circuits_Conference" title="International Solid-State Circuits Conference">ISSCC</a> 2011, Intel presented a paper called "A 32nm 3.1 Billion Transistor 12-Wide-Issue Itanium Processor for Mission Critical Servers."<a href="#cite_note-dx.doi.org-123">[119]</a><a href="#cite_note-124">[120]</a>

Analyst David Kanter speculated that Poulson would use a new microarchitecture, with a more advanced form of multithreading that uses up to two threads, to improve performance for single threaded and multithreaded workloads.<a href="#cite_note-125">[121]</a>

Some information was also released at the <a href="Hot_Chips" class="mw-redirect" title="Hot Chips">Hot Chips</a> conference.<a href="#cite_note-126">[122]</a><a href="#cite_note-127">[123]</a>

Information presented improvements in multithreading, resiliency improvements (<a href="Intel_Instruction_Replay" class="mw-redirect" title="Intel Instruction Replay">Intel Instruction Replay</a> RAS) and few new instructions (thread priority, integer instruction, cache prefetching, and data access hints).

Poulson was released on November 8, 2012, as the Itanium 9500 series processor. It is the follow-on processor to Tukwila. It features eight cores and has a 12-wide issue architecture, multithreading enhancements, and new instructions to take advantage of parallelism, especially in virtualization.<a href="#cite_note-Kittson-116">[112]</a><a href="#cite_note-poulson-the-future-of-itanium-servers-128">[124]</a><a href="#cite_note-HotChip-Poulson-129">[125]</a>

The Poulson L3 cache size is 32 MB and common for all cores, not divided like previously. L2 cache size is 6 MB, 512 I <a href="Kibibyte" class="mw-redirect" title="Kibibyte">KB</a>, 256 D KB per core.<a href="#cite_note-dx.doi.org-123">[119]</a> Die size is 544 mm², less than its predecessor Tukwila (698.75 mm²).<a href="#cite_note-130">[126]</a><a href="#cite_note-131">[127]</a>

Intel's Product Change Notification (PCN) 111456-01 lists four models of Itanium 9500 series <a href="Central_processing_unit" title="Central processing unit">CPU</a>, which was later removed in a revised document.<a href="#cite_note-cpu-world.com-132">[128]</a> The parts were later listed in Intel's Material Declaration Data Sheets (MDDS) database.<a href="#cite_note-133">[129]</a> Intel later posted Itanium 9500 reference manual.<a href="#cite_note-134">[130]</a>

The models are the following:<a href="#cite_note-cpu-world.com-132">[128]</a><a href="#cite_note-135">[131]</a>

<th>Processor number</th>

<th>Frequency</th>

<th>Cache

</th></tr>

<tr>

<td>20MB

</td></tr>

<tr>

<td>24MB

</td></tr>

<tr>

<td>32MB

</td></tr>

<tr>

<td>32MB

</td></tr></tbody></table></dd></dl>

<div class="mw-heading mw-heading3"><h3 id="Itanium_9700_(Kittson):_2017">Itanium 9700 (Kittson): 2017</h3></div>

Intel had committed to at least one more generation after Poulson, first mentioning Kittson on 14 June 2007.<a href="#cite_note-mercury-122">[118]</a> Kittson was supposed to be on a 22 nm process and use the same <a href="LGA2011" class="mw-redirect" title="LGA2011">LGA2011</a> socket and platform as <a href="Xeon" title="Xeon">Xeons</a>.<a href="#cite_note-136">[132]</a><a href="#cite_note-137">[133]</a><a href="#cite_note-138">[134]</a> On 31 January 2013 Intel issued an update to their plans for Kittson: it would have the same <a href="LGA1248" class="mw-redirect" title="LGA1248">LGA1248</a> socket and 32 nm process as Poulson, thus effectively halting any further development of Itanium processors.<a href="#cite_note-139">[135]</a>

In April 2015, Intel, although it had not yet confirmed formal specifications, did confirm that it continued to work on the project.<a href="#cite_note-kitguru-140">[136]</a> Meanwhile, the aggressively multicore Xeon E7 platform displaced Itanium-based solutions in the Intel roadmap.<a href="#cite_note-141">[137]</a> Even <a href="Hewlett-Packard" title="Hewlett-Packard">Hewlett-Packard</a>, the main proponent and customer for Itanium, began selling <a href="X86" title="X86">x86</a>-based <a href="HP_Superdome" class="mw-redirect" title="HP Superdome">Superdome</a> and <a href="NonStop_(server_computers)" title="NonStop (server computers)">NonStop</a> servers, and started to treat the Itanium-based versions as legacy products.<a href="#cite_note-142">[138]</a><a href="#cite_note-143">[139]</a>

Intel officially launched the Itanium 9700 series processor family on May 11, 2017.<a href="#cite_note-144">[140]</a><a href="#cite_note-IA-PCWorld-10">[8]</a> Kittson has no microarchitecture improvements over Poulson; despite nominally having a different stepping, it is functionally identical with the 9500 series, even having exactly the same bugs, the only difference being the 133 MHz higher frequency of 9760 and 9750 over 9560 and 9550 respectively.<a href="#cite_note-145">[141]</a><a href="#cite_note-146">[142]</a>

Intel announced that the 9700 series would be the last Itanium chips produced.<a href="#cite_note-Davis_2017-9">[7]</a><a href="#cite_note-IA-PCWorld-10">[8]</a>

The models are:<a href="#cite_note-147">[143]</a>

<th>Processor number</th>

<th>Cores</th>

<th>Threads</th>

<th>Frequency</th>

<th>Cache

</th></tr>

<tr>

<td>20 MB

</td></tr>

<tr>

<td>24 MB

</td></tr>

<tr>

<td>32 MB

</td></tr>

<tr>

<td>32 MB

</td></tr></tbody></table></dd></dl>

<div class="mw-heading mw-heading2"><h2 id="Market_share">Market share</h2></div>

Compared to its <a href="Xeon" title="Xeon">Xeon</a> family of server processors, Itanium was never a high-volume product for Intel. Intel does not release production numbers, but one industry analyst estimated that the production rate was 200,000 processors per year in 2007.<a href="#cite_note-148">[144]</a>

According to <a href="Gartner_Inc." class="mw-redirect" title="Gartner Inc.">Gartner Inc.</a>, the total number of Itanium servers (not processors) sold by all vendors in 2007, was about 55,000 (It is unclear whether clustered servers counted as a single server or not.). This compares with 417,000 RISC servers (spread across all RISC vendors) and 8.4 million x86 servers. <a href="International_Data_Corporation" class="mw-redirect" title="International Data Corporation">IDC</a> reports that a total of 184,000 Itanium-based systems were sold from 2001 through 2007. For the combined POWER/SPARC/Itanium systems market, IDC reports that POWER captured 42% of revenue and SPARC captured 32%, while Itanium-based system revenue reached 26% in the second quarter of 2008.<a href="#cite_note-149">[145]</a>

According to an IDC analyst, in 2007, HP accounted for perhaps 80% of Itanium systems revenue.<a href="#cite_note-CW1-98">[94]</a>

According to Gartner, in 2008, HP accounted for 95% of Itanium sales.<a href="#cite_note-vance_late-150">[146]</a> HP's Itanium system sales were at an annual rate of $4.4Bn at the end of 2008, and declined to $3.5Bn by the end of 2009,<a href="#cite_note-Gartner_2009-q4-12">[10]</a>

compared to a 35% decline in UNIX system revenue for Sun and an 11% drop for IBM, with an x86-64 server revenue increase of 14% during this period.

In December 2012, IDC released a research report stating that Itanium server shipments would remain flat through 2016, with annual shipment of 26,000 systems (a decline of over 50% compared to shipments in 2008).<a href="#cite_note-151">[147]</a>

<div class="mw-heading mw-heading2"><h2 id="Hardware_support">Hardware support</h2></div>

<div class="mw-heading mw-heading3"><h3 id="Systems">Systems</h3></div>

<caption>Server manufacturers' Itanium products

</caption>

<th colspan="3">Company

</th>

<th colspan="2">Last product

</th></tr>

<tr>

<th>CPUs

</th></tr>

<tr>

<td><a href="HPE_Integrity_Servers" title="HPE Integrity Servers">Integrity</a></td>

<td>1–256

</td></tr>

<tr>

<td><a href="Compaq" title="Compaq">Compaq</a></td>

<td>2001

</td>

<td><a href="ProLiant" title="ProLiant">ProLiant</a> 590</td>

<td>1–4

</td></tr>

<tr>

<td><a href="Lenovo_System_x" title="Lenovo System x">System x</a>455</td>

<td>1–16

</td></tr>

<tr>

<td><a href="Dell_PowerEdge" class="mw-redirect" title="Dell PowerEdge">PowerEdge</a> 7250</td>

<td>1–4

</td></tr>

<tr>

<td><a href="Hitachi" title="Hitachi">Hitachi</a></td>

<td>BladeSymphony 1000</td>

<td>1–8

</td></tr>

<tr>

<td><a href="Unisys" title="Unisys">Unisys</a></td>

<td>1–32

</td></tr>

<tr>

<td><a href="Altix" title="Altix">Altix</a> 4000</td>

<td>1–2048

</td></tr>

<tr>

<td><a href="Fujitsu" title="Fujitsu">Fujitsu</a></td>

<td>PRIMEQUEST</td>

<td>1–32

</td></tr>

<tr>

<td>NovaScale 9410</td>

<td>1–32

</td></tr>

<tr>

<td>1–256

</td></tr>

<tr>

<td><a href="Inspur" title="Inspur">Inspur</a></td>

<td>2–1024

</td></tr>

<tr>

<td><a href="Huawei" title="Huawei">Huawei</a></td>

<td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">?

</td></tr></tbody></table>

By 2006, HP manufactured at least 80% of all Itanium systems, and sold 7,200 in the first quarter of 2006.<a href="#cite_note-152">[148]</a>

The bulk of systems sold were <a href="Enterprise_server" class="mw-redirect" title="Enterprise server">enterprise servers</a> and machines for large-scale technical computing, with an average selling price per system in excess of US$200,000. A typical system used eight or more Itanium processors.

By 2012, only a few manufacturers offered Itanium systems, including <a href="Hewlett-Packard" title="Hewlett-Packard">HP</a>, <a href="Groupe_Bull" title="Groupe Bull">Bull</a>, <a href="NEC" title="NEC">NEC</a>, <a href="Inspur" title="Inspur">Inspur</a> and <a href="Huawei" title="Huawei">Huawei</a>. In addition, <a href="Intel" title="Intel">Intel</a> offered a chassis that could be used by <a href="System_integrator" class="mw-redirect" title="System integrator">system integrators</a> to build Itanium systems.<a href="#cite_note-153">[149]</a>

By 2015, only HP supplied Itanium-based systems.<a href="#cite_note-kitguru-140">[136]</a> When HP split in late 2015, Itanium systems (branded as <a href="HPE_Integrity_Servers" title="HPE Integrity Servers">Integrity</a>)<a href="#cite_note-eol-154">[150]</a> were handled by <a href="Hewlett_Packard_Enterprise" title="Hewlett Packard Enterprise">Hewlett Packard Enterprise</a> (HPE), with a major update in 2017 (Integrity i6, and HP-UX 11i v3 Update 16). HPE also supports a few other operating systems, including <a href="Windows" class="mw-redirect" title="Windows">Windows</a> up to Server 2008 R2, <a href="Linux" title="Linux">Linux</a>, <a href="OpenVMS" title="OpenVMS">OpenVMS</a> and <a href="NonStop_(server_computers)" title="NonStop (server computers)">NonStop</a>. Itanium is not affected by <a href="Spectre_(security_vulnerability)" title="Spectre (security vulnerability)">Spectre</a> or <a href="Meltdown_(security_vulnerability)" title="Meltdown (security vulnerability)">Meltdown</a>.<a href="#cite_note-155">[151]</a>

<div class="mw-heading mw-heading3"><h3 id="Chipsets">Chipsets</h3></div>

Prior to the 9300-series (<a href="Tukwila_(processor)" title="Tukwila (processor)">Tukwila</a>), chipsets were needed to connect to the main memory and I/O devices, as the <a href="Front-side_bus" title="Front-side bus">front-side bus</a> to the <a href="Chipset" title="Chipset">chipset</a> was the sole operational connection to the processor.<a href="#cite_note-156">[e]</a> Two generations of buses existed: the original Itanium processor system bus (a.k.a. Merced bus) had a 64 bit data width and 133 MHz clock with <a href="Double_data_rate" title="Double data rate">DDR</a> (266 MT/s), being soon superseded by the 128-bit 200 MHz DDR (400 MT/s) Itanium 2 processor system bus (a.k.a. McKinley bus), which later reached 533 and 667 MT/s. Up to four CPUs per single bus could be used, but prior to the 9000-series the bus speeds of over 400 MT/s were limited to up to two processors per bus.<a href="#cite_note-157">[152]</a><a href="#cite_note-158">[153]</a> As no Itanium chipset could connect to more than four sockets, high-end servers needed multiple interconnected chipsets.

The "Tukwila" Itanium processor model had been designed to share a common chipset with the Intel Xeon processor EX (Intel's Xeon processor designed for four processor and larger servers). The goal was to streamline system development and reduce costs for server OEMs, many of which develop both Itanium- and Xeon-based servers. However, in 2013, this goal was pushed back to be "evaluated for future implementation opportunities".<a href="#cite_note-159">[154]</a>

In the times before on-chip memory controllers and <a href="QPI" class="mw-redirect" title="QPI">QPI</a>, enterprise server manufacturers differentiated their systems by designing and developing chipsets that interface the processor to memory, interconnections, and peripheral controllers. "Enterprise server" referred to the then-lucrative market segment of high-end servers with high <a href="Reliability%2C_availability_and_serviceability" title="Reliability, availability and serviceability">reliability, availability and serviceability</a> and typically 16+ processor sockets, justifying their pricing by having a custom system-level architecture with their own chipsets at its heart, with capabilities far beyond what two-socket "commodity servers" could offer. Development of a chipset costs tens of millions of dollars and so represented a major commitment to the use of Itanium.

Neither Intel nor IBM would develop Itanium 2 chipsets to support newer technologies such as <a href="DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a> or <a href="PCI_Express" title="PCI Express">PCI Express</a>.<a href="#cite_note-ibm_ditching_itanium-160">[155]</a>

Before "Tukwila" moved away from the FSB, chipsets supporting such technologies were manufactured by all Itanium server vendors, such as HP, Fujitsu, SGI, NEC, and Hitachi.

<div class="mw-heading mw-heading4"><h4 id="Intel">Intel</h4></div>

The first generation of Itanium received no vendor-specific chipsets, only Intel's 460GX consisting of ten distinct chips. It supported up to four CPUs and 64 GB of memory at 4.2 GB/s, which is twice the system bus's bandwidth. Addresses and data were handled by two different chips. 460GX had an <a href="Accelerated_Graphics_Port" title="Accelerated Graphics Port">AGP</a> X4 graphics bus, two 64-bit 66 MHz <a href="Peripheral_Component_Interconnect" title="Peripheral Component Interconnect">PCI</a> buses and configurable 33 MHz dual 32-bit or single 64-bit PCI bus(es).<a href="#cite_note-161">[156]</a>

There were many custom chipset designs for Itanium 2, but many smaller vendors chose to use Intel's E8870 chipset. It supports 128 GB of <a href="DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a> at 6.4 GB/s. It was originally designed for <a href="Rambus" title="Rambus">Rambus</a> <a href="RDRAM" title="RDRAM">RDRAM</a> <a href="Serial_communication" title="Serial communication">serial</a> memory, but when RDRAM failed, Intel added four DDR SDRAM-to-RDRAM converter chips to the chipset.<a href="#cite_note-162">[157]</a> When Intel had previously made such a converter for Pentium III chipsets 820 and 840, it drastically cut performance.<a href="#cite_note-163">[158]</a><a href="#cite_note-164">[159]</a> E8870 provides eight 133 MHz <a href="PCI-X" title="PCI-X">PCI-X</a> buses (4.2 GB/s total because of bottlenecks) and a <a href="I/O_Controller_Hub#ICH4" title="I/O Controller Hub">ICH4</a> hub with six <a href="USB_2.0" class="mw-redirect" title="USB 2.0">USB 2.0</a> ports.

Two E8870 can be linked together by two E8870SP Scalability Port Switches, each containing a 1MB (~200,000 cache lines) <a href="Bus_snooping#Snoop_filter" title="Bus snooping">snoop filter</a>, to create an 8-socket system with double the memory and PCI-X capacity, but still only one ICH4. Further expansion to 16 sockets was planned.<a href="#cite_note-165">[160]</a><a href="#cite_note-166">[161]</a><a href="#cite_note-167">[162]</a> In 2004 Intel revealed plans for its next Itanium chipset, codenamed Bayshore, to support <a href="PCI-e" class="mw-redirect" title="PCI-e">PCI-e</a> and <a href="DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a> memory, but canceled it the same year.<a href="#cite_note-168">[163]</a><a href="#cite_note-ibm_ditching_itanium-160">[155]</a>

<div class="mw-heading mw-heading4"><h4 id="Hewlett-Packard">Hewlett-Packard</h4></div>

HP has designed four different chipsets for Itanium 2: zx1, sx1000, zx2 and sx2000. All support 4 sockets per chipset, but sx1000 and sx2000 support interconnection of up to 16 chipsets to create up to a 64 socket system. As it was developed in collaboration with Itanium 2's development, booting the first Itanium 2 in February 2001,<a href="#cite_note-169">[164]</a> zx1 became the first Itanium 2 chipset available and later in 2004 also the first to support 533 MT/s FSB. In its basic two-chip version it directly provides four channels of <a href="DDR_SDRAM" title="DDR SDRAM">DDR-266</a> memory, giving 8.5 GB/s of bandwidth and 32 GB of capacity (though 12 DIMM slots).<a href="#cite_note-170">[165]</a> In versions with memory expander boards memory bandwidth reaches 12.8 GB/s, while the maximum capacity for the initial two-board 48 DIMM expanders was 96 GB, and the later single-board 32 DIMM expander up to 128 GB. The memory latency increases by 25 nanoseconds from 80 ns due to the expanders. Eight independent links went to the PCI-X and other peripheral devices (e.g. <a href="Accelerated_Graphics_Port" title="Accelerated Graphics Port">AGP</a> in workstations), totaling 4 GB/s.<a href="#cite_note-171">[166]</a><a href="#cite_note-172">[167]</a>

HP's first high-end Itanium chipset was sx1000, launched in mid-2003 with the <a href="HP_Superdome" class="mw-redirect" title="HP Superdome">Integrity Superdome</a> flagship server.

It has two independent front-side buses, each bus supporting two sockets, giving 12.8 GB/s of combined bandwidth from the processors to the chipset. It has four links to data-only memory buffers and supports 64 GB of HP-designed 125 MHz memory at 16 GB/s. The above components form a system board called a cell. Two cells can be directly connected together to create an 8-socket <a href="Glue_logic" title="Glue logic">glueless</a> system. To connect four cells together, a pair of 8-ported <a href="Crossbar_switch" title="Crossbar switch">crossbar switches</a> is needed (adding 64 <a href="Nanosecond" title="Nanosecond">ns</a> to inter-cell memory accesses), while four such pairs of crossbar switches are needed for the top-end system of 16 cells (64 sockets), giving 32 GB/s of <a href="Bisection_bandwidth" title="Bisection bandwidth">bisection bandwidth</a>. Cells maintain cache coherence through in-memory <a href="Directory-based_cache_coherence" title="Directory-based cache coherence">directories</a>, which causes the minimum memory latency to be 241 ns. The latency to the most remote (<a href="Non-uniform_memory_access" title="Non-uniform memory access">NUMA</a>) memory is 463 ns. The per-cell bandwidth to the I/O subsystems is 2 GB/s, despite the presence of 8 GB/s worth of PCI-X buses in each I/O subsystem.<a href="#cite_note-173">[168]</a><a href="#cite_note-174">[169]</a><a href="#cite_note-175">[170]</a>

HP launched sx2000 in March 2006 to succeed sx1000. Its two FSBs operate at 533 MT/s. It supports up to 128 GB of memory at 17 GB/s. The memory is of HP's custom design, using the <a href="DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a> protocol, but twice as tall as the standard modules and with redundant address and control signal contacts. For the inter-chipset communication, 25.5 GB/s is available on each sx2000 through its three <a href="Serial_communication" title="Serial communication">serial</a> links that can connect to a set of three <a href="Redundancy_(engineering)" title="Redundancy (engineering)">independent</a> <a href="Crossbar_switch" title="Crossbar switch">crossbars</a>, which connect to other cells or up to 3 other sets of 3 crossbars. The multi-cell configurations are the same as with sx1000, except the parallelism of the sets of crossbars has been increased from 2 to 3. The maximum configuration of 64 sockets has 72 GB/s of sustainable <a href="Bisection_bandwidth" title="Bisection bandwidth">bisection bandwidth</a>. The chipset's connection to its I/O module is now serial with an 8.5 GB/s peak and 5.5 GB/s sustained bandwidth, the I/O module having either 12 <a href="PCI-X" title="PCI-X">PCI-X</a> buses at up to 266 MHz, or 6 PCI-X buses and 6 <a href="PCIe" class="mw-redirect" title="PCIe">PCIe</a> 1.1 ×8 slots. It is the last chipset to support HP's <a href="PA-RISC" title="PA-RISC">PA-RISC</a> processors (<a href="PA-8000#PA-8900" title="PA-8000">PA-8900</a>).<a href="#cite_note-176">[171]</a>

HP launched the first zx2-based servers in September 2006. zx2 can operate the FSB at 667 MT/s with two CPUs or 533 MT/s with four CPUs. It connects to the <a href="DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a> memory either directly, supporting 32 GB at up to 14.2 GB/s, or through expander boards, supporting up to 384 GB at 17 GB/s. The minimum open-page latency is 60 to 78 ns. 9.8 GB/s are available through eight independent links to the I/O adapters, which can include PCIe ×8 or 266 MHz PCI-X.<a href="#cite_note-177">[172]</a><a href="#cite_note-178">[173]</a>

<div class="mw-heading mw-heading4"><h4 id="Others">Others</h4></div>

In May 2003, IBM launched the XA-64 chipset for Itanium 2. It used many of the same technologies as the first two generations of XA-32 chipsets for <a href="Xeon" title="Xeon">Xeon</a>, but by the time of the third gen XA-32 IBM had decided to discontinue its Itanium products. XA-64 supported 56 GB of <a href="DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a> in 28 slots at 6.4 GB/s, though due to bottlenecks only 3.2 GB/s could go to the CPU and other 2 GB/s to devices for a 5.2 GB/s total. The CPU's memory bottleneck was mitigated by an off-chip 64 MB <a href="DRAM" class="mw-redirect" title="DRAM">DRAM</a> L4 cache, which also worked as a <a href="Bus_snooping#Snoop_filter" title="Bus snooping">snoop filter</a> in multi-chipset systems. The combined bandwidth of the four <a href="PCI-X" title="PCI-X">PCI-X</a> buses and other I/O is bottlenecked to 2 GB/s per chipset. Two or four chipsets can be connected to make an 8 or 16 socket system.<a href="#cite_note-179">[174]</a>

<a href="Silicon_Graphics" title="Silicon Graphics">SGI</a>'s <a href="Altix" title="Altix">Altix</a> supercomputers and servers used the SHUB (Super-Hub) chipset, which supports two Itanium 2 sockets. The initial version used <a href="DDR_SDRAM" title="DDR SDRAM">DDR memory</a> through four buses for up to 12.8 GB/s bandwidth, and up to 32 GB of capacity across 16 slots. A 2.4 GB/s <a href="XIO" title="XIO">XIO</a> channel connected to a module with up to six 64-bit 133 MHz <a href="PCI-X" title="PCI-X">PCI-X</a> buses. SHUBs can be interconnected by the dual 6.4 GB/s <a href="NUMAlink" title="NUMAlink">NUMAlink</a>4 link planes to create a 512-socket cache-coherent single-image system. A cache for the in-memory <a href="Directory-based_cache_coherence" title="Directory-based cache coherence">coherence directory</a> saves memory bandwidth and reduces latency. The latency to the local memory is 132 ns, and each crossing of a NUMAlink4 router adds 50 ns. I/O modules with four 133 MHz PCI-X buses can connect directly to the NUMAlink4 network.<a href="#cite_note-180">[175]</a><a href="#cite_note-181">[176]</a><a href="#cite_note-182">[177]</a><a href="#cite_note-183">[178]</a> SGI's second-generation SHUB 2.0 chipset supported up to 48 GB of <a href="DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a> memory, 667 MT/s FSB, and could connect to I/O modules providing <a href="PCI_Express" title="PCI Express">PCI Express</a>.<a href="#cite_note-184">[179]</a><a href="#cite_note-185">[180]</a> It supports only four local threads, so when having two dual-core CPUs per chipset, <a href="Hyper-Threading" class="mw-redirect" title="Hyper-Threading">Hyper-Threading</a> must be disabled.<a href="#cite_note-186">[181]</a>

<div class="mw-heading mw-heading2"><h2 id="Software_support">Software support</h2></div>

<ul><li><a href="HP-UX" title="HP-UX">HP-UX</a> 11 (supported until 2025)</li></ul>

<ul><li><a href="NetBSD" title="NetBSD">NetBSD</a> (a tier II port<a href="#cite_note-187">[182]</a> that "is a work-in-progress effort to port NetBSD to the Itanium family of processors. Currently no formal release is available."<a href="#cite_note-188">[183]</a>)</li>

<li><a href="FreeBSD" title="FreeBSD">FreeBSD</a> (unsupported since 31 October 2018)</li></ul>

<div class="mw-heading mw-heading3"><h3 id="Linux">Linux</h3></div>

The Trillian Project was an effort by an industry consortium to port the <a href="Linux" title="Linux">Linux</a> kernel to the Itanium processor. The project started in May 1999 with the goal of releasing the distribution in time for the initial release of Itanium, then scheduled for early 2000.<a href="#cite_note-Sabbagh-189">[184]</a> By the end of 1999, the project included <a href="Caldera_Systems" class="mw-redirect" title="Caldera Systems">Caldera Systems</a>, <a href="CERN" title="CERN">CERN</a>, <a href="Cygnus_Solutions" title="Cygnus Solutions">Cygnus Solutions</a>, <a href="Hewlett-Packard" title="Hewlett-Packard">Hewlett-Packard</a>, <a href="IBM" title="IBM">IBM</a>, <a href="Intel" title="Intel">Intel</a>, <a href="Red_Hat" title="Red Hat">Red Hat</a>, <a href="Silicon_Graphics" title="Silicon Graphics">SGI</a>, <a href="SUSE_S.A." title="SUSE S.A.">SuSE</a>, <a href="TurboLinux" class="mw-redirect" title="TurboLinux">TurboLinux</a> and <a href="VA_Linux_Systems" class="mw-redirect" title="VA Linux Systems">VA Linux Systems</a>.<a href="#cite_note-190">[185]</a> The project released the resulting code in February 2000.<a href="#cite_note-Sabbagh-189">[184]</a> The code then became part of the <a href="Mainline_Linux_kernel" class="mw-redirect" title="Mainline Linux kernel">mainline Linux kernel</a> more than a year before the release of the first Itanium processor. The Trillian project was able to do this for two reasons:

<ul><li>the <a href="Free_software" title="Free software">free</a> and <a href="Open_source_software" class="mw-redirect" title="Open source software">open source</a> <a href="GNU_Compiler_Collection" title="GNU Compiler Collection">GCC</a> compiler had already been enhanced to support the Itanium architecture.</li>

<li>a free and open source simulator had been developed to simulate an Itanium processor on an existing computer.<a href="#cite_note-191">[186]</a></li></ul>

After the successful completion of Project Trillian, the resulting Linux kernel was used by all of the manufacturers of Itanium systems (<a href="Hewlett-Packard" title="Hewlett-Packard">HP</a>, <a href="IBM" title="IBM">IBM</a>, <a href="Dell" title="Dell">Dell</a>, <a href="Silicon_Graphics" title="Silicon Graphics">SGI</a>, <a href="Fujitsu" title="Fujitsu">Fujitsu</a>, <a href="Unisys" title="Unisys">Unisys</a>, <a href="Hitachi" title="Hitachi">Hitachi</a>, and <a href="Groupe_Bull" title="Groupe Bull">Groupe Bull</a>). With the notable exception of HP, Linux is either the primary OS or the only OS the manufacturer supports for Itanium. Ongoing free and open source software support for Linux on Itanium subsequently coalesced at <a href="Gelato_Federation" title="Gelato Federation">Gelato</a>.

<div class="mw-heading mw-heading4"><h4 id="Distribution_support">Distribution support</h4></div>

In 2005, Fedora Linux started adding support for Itanium<a href="#cite_note-192">[187]</a> and Novell added support for SUSE Linux.<a href="#cite_note-193">[188]</a> In 2007, <a href="CentOS" title="CentOS">CentOS</a> added support for Itanium in a new release.<a href="#cite_note-194">[189]</a>

<ul><li><a href="Debian" title="Debian">Debian</a> (official support was dropped in Debian 8; unofficial support available through Debian Ports until June 2024<a href="#cite_note-195">[190]</a>)</li>

<li>EPIC Slack - an unofficial port of <a href="Slackware" title="Slackware">Slackware</a> - specifically supports <a href="IA-64" title="IA-64">IA-64</a> (and hence Itanium) since its release in May 2024.<a href="#cite_note-196">[191]</a></li>

<li><a href="Gentoo_Linux" title="Gentoo Linux">Gentoo Linux</a><a href="#cite_note-197">[192]</a> (releases before August 2024)<a href="#cite_note-198">[193]</a></li>

<li><a href="Red_Hat_Enterprise_Linux" title="Red Hat Enterprise Linux">Red Hat Enterprise Linux</a> (unsupported since RHEL 6, had support in RHEL 5 until 2017, which supported other platforms until November 30, 2020)</li>

<li><a href="SUSE_Linux_Enterprise_Server" class="mw-redirect" title="SUSE Linux Enterprise Server">SUSE Linux</a> 11 (supported until 2019, for other platforms SUSE 11 was supported until 2022).</li>

<li><a href="T2_SDE" title="T2 SDE">T2 SDE</a> supports Itanium in its <a href="IA-64" title="IA-64">IA-64</a> port.<a href="#cite_note-199">[194]</a></li></ul>

<div class="mw-heading mw-heading4"><h4 id="Deprecation">Deprecation</h4></div>

In 2009, Red Hat dropped Itanium support in Enterprise Linux 6.<a href="#cite_note-red-hat-to-drop-itanium-200">[195]</a> Ubuntu 10.10 dropped support for Itanium.<a href="#cite_note-201">[196]</a> In 2021, Linus Torvalds marked the Itanium code as orphaned. Torvalds said:

"HPE no longer accepts orders for new Itanium hardware, and Intel stopped accepting orders a year ago. While intel is still officially shipping chips until July 29, 2021, it's unlikely that any such orders actually exist. <a href="He's_dead%2C_Jim" class="mw-redirect" title="He's dead, Jim">It's dead, Jim</a>."<a href="#cite_note-202">[197]</a><a href="#cite_note-203">[198]</a>

Support for Itanium was removed in Linux 6.7<a href="#cite_note-204">[199]</a><a href="#cite_note-205">[200]</a> and is since then maintained <a href="https://en.wiktionary.org/wiki/out-of-tree" class="extiw external" title="wiktionary:out-of-tree">out-of-tree</a>.<a href="#cite_note-206">[201]</a><a href="#cite_note-207">[202]</a>

<div class="mw-heading mw-heading3"><h3 id="Microsoft_Windows">Microsoft Windows</h3></div>

<ul><li><a href="Windows_XP_64-Bit_Edition" class="mw-redirect" title="Windows XP 64-Bit Edition">Windows XP 64-Bit Edition</a> (unsupported since June 30, 2005)</li>

<li><a href="Windows_Server_2003" title="Windows Server 2003">Windows Server 2003</a> (unsupported since July 14, 2015)</li>

<li><a href="Windows_Server_2008" title="Windows Server 2008">Windows Server 2008</a> (unsupported since January 14, 2020, paid Extended Security Updates not available on Itanium)</li>

<li><a href="Windows_Server_2008_R2" title="Windows Server 2008 R2">Windows Server 2008 R2</a> (unsupported since January 14, 2020, paid Extended Security Updates not available on Itanium; last Windows version to support Itanium processors)</li></ul>

<div class="mw-heading mw-heading3"><h3 id="OpenVMS">OpenVMS</h3></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="OpenVMS#Port_to_Intel_Itanium" title="OpenVMS">OpenVMS § Port to Intel Itanium</a></div>

In 2001, <a href="Compaq" title="Compaq">Compaq</a> announced that OpenVMS would be ported to the Itanium architecture.<a href="#cite_note-208">[203]</a> This led to the creation of the V8.x releases of OpenVMS, which support both Itanium-based <a href="HPE_Integrity_Servers" title="HPE Integrity Servers">HPE Integrity Servers</a> and <a href="DEC_Alpha" title="DEC Alpha">DEC Alpha</a> hardware.<a href="#cite_note-ia64-port-209">[204]</a> Since the Itanium porting effort began, ownership of OpenVMS transferred from Compaq to HP in 2001, and then to VMS Software Inc. (VSI) in 2014.<a href="#cite_note-VSI.CW2014-210">[205]</a> Noteworthy releases include:

<ul><li>V8.0 (2003) - First pre-production release of OpenVMS on Itanium available outside HP.<a href="#cite_note-ia64-port-209">[204]</a></li>

<li>V8.2 (2005) - First production-grade release of OpenVMS on Itanium.<a href="#cite_note-ia64-port-209">[204]</a></li>

<li>V8.4 (2010) - Final release of OpenVMS supported by HP. Support ended on December 31, 2020.<a href="#cite_note-211">[206]</a></li>

<li>V8.4-2L3 (2021) - Final release of OpenVMS on Itanium supported by VSI. Support ends on December 31, 2035.<a href="#cite_note-vsi-roadmap-212">[207]</a></li></ul>

Support for Itanium has been dropped in the V9.x releases of OpenVMS, which run on x86-64 only.<a href="#cite_note-vsi-roadmap-212">[207]</a>

<div class="mw-heading mw-heading3"><h3 id="NonStop_OS">NonStop OS</h3></div>

<a href="NonStop_OS" class="mw-redirect" title="NonStop OS">NonStop OS</a> was ported from <a href="MIPS_architecture" title="MIPS architecture">MIPS</a>-based hardware to Itanium in 2005.<a href="#cite_note-213">[208]</a> NonStop OS was later ported to x86-64 in 2015. Sales of Itanium-based NonStop hardware ended in 2020, with support ending in 2025.<a href="#cite_note-hpe-brochure-214">[209]</a><a href="#cite_note-215">[210]</a>

<div class="mw-heading mw-heading3"><h3 id="Compiler">Compiler</h3></div>

<a href="GNU_Compiler_Collection" title="GNU Compiler Collection">GNU Compiler Collection</a> deprecated support for IA-64 in GCC 10, after Intel announced the planned phase-out of this ISA.<a href="#cite_note-216">[211]</a> <a href="LLVM" title="LLVM">LLVM</a> (Clang) dropped Itanium support in version 2.6.<a href="#cite_note-217">[212]</a>

<div class="mw-heading mw-heading3"><h3 id="Virtualization_and_emulation">Virtualization and emulation</h3></div>

HP sells a <a href="OS-level_virtualization" title="OS-level virtualization">virtualization</a> technology for Itanium called <a href="HP_Integrity_Virtual_Machines" title="HP Integrity Virtual Machines">Integrity Virtual Machines</a>.

<a href="Emulator" title="Emulator">Emulation</a> is a technique that allows a computer to execute binary code that was compiled for a different type of computer. Before IBM's acquisition of <a href="QuickTransit" title="QuickTransit">QuickTransit</a> in 2009, application binary software for <a href="IRIX" title="IRIX">IRIX</a>/<a href="MIPS_architecture" title="MIPS architecture">MIPS</a> and <a href="Solaris_(operating_system)" class="mw-redirect" title="Solaris (operating system)">Solaris</a>/<a href="SPARC" title="SPARC">SPARC</a> could run via type of emulation called "dynamic binary translation" on Linux/Itanium. Similarly, HP implemented a method to execute PA-RISC/HP-UX on the Itanium/HP-UX via emulation, to simplify migration of its PA-RISC customers to the radically different Itanium instruction set. Itanium processors can also run the mainframe environment <a href="General_Comprehensive_Operating_System" title="General Comprehensive Operating System">GCOS</a> from <a href="Groupe_Bull" title="Groupe Bull">Groupe Bull</a> and several <a href="X86" title="X86">x86</a> operating systems via <a href="Instruction_set_simulator" title="Instruction set simulator">instruction set simulators</a>.

<div class="mw-heading mw-heading2"><h2 id="Competition">Competition</h2></div>

Itanium was aimed at the <a href="Enterprise_server" class="mw-redirect" title="Enterprise server">enterprise server</a> and <a href="High-performance_computing" title="High-performance computing">high-performance computing</a> (HPC) markets. Other enterprise- and HPC-focused processor lines include <a href="Oracle_Corporation" title="Oracle Corporation">Oracle</a>'s and <a href="Fujitsu" title="Fujitsu">Fujitsu</a>'s <a href="SPARC" title="SPARC">SPARC</a> processors and <a href="IBM" title="IBM">IBM</a>'s <a href="IBM_Power_microprocessors" title="IBM Power microprocessors">Power microprocessors</a>. Measured by quantity sold, Itanium's most serious competition came from <a href="X86-64" title="X86-64">x86-64</a> processors including <a href="Intel" title="Intel">Intel</a>'s own <a href="Xeon" title="Xeon">Xeon</a> line and <a href="Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">AMD</a>'s <a href="Opteron" title="Opteron">Opteron</a> line. Since 2009, most servers were being shipped with x86-64 processors.<a href="#cite_note-Gartner_2009-q4-12">[10]</a>

In 2005, Itanium systems accounted for about 14% of HPC systems revenue, but the percentage declined as the industry shifted to x86-64 clusters for this application.<a href="#cite_note-218">[213]</a>

An October 2008 <a href="Gartner" title="Gartner">Gartner</a> report on the Tukwila processor stated that "...the future roadmap for Itanium looks as strong as that of any RISC peer like Power or SPARC."<a href="#cite_note-219">[214]</a>

<div class="mw-heading mw-heading2"><h2 id="Supercomputers_and_high-performance_computing">Supercomputers and high-performance computing</h2></div>

An Itanium-based computer first appeared on the list of the <a href="TOP500" title="TOP500">TOP500</a> <a href="Supercomputer" title="Supercomputer">supercomputers</a> in November 2001.<a href="#cite_note-Thunder-79">[75]</a> The best position ever achieved by an Itanium 2 based system in the list was No. 2, achieved in June 2004, when Thunder (<a href="Lawrence_Livermore_National_Laboratory" title="Lawrence Livermore National Laboratory">Lawrence Livermore National Laboratory</a>) entered the list with an Rmax of 19.94 Teraflops. In November 2004, <a href="Columbia_(supercomputer)" title="Columbia (supercomputer)">Columbia</a> entered the list at No. 2 with 51.8 Teraflops, and there was at least one Itanium-based computer in the top 10 from then until June 2007. The peak number of Itanium-based machines on the list occurred in the November 2004 list, at 84 systems (16.8%); by June 2012, this had dropped to one system (0.2%),<a href="#cite_note-220">[215]</a> and no Itanium system remained on the list in November 2012.

<div class="mw-heading mw-heading2"><h2 id="Processors">Processors</h2></div>

<div class="mw-heading mw-heading3"><h3 id="Released_processors">Released processors</h3></div>

The Itanium processors show a progression in capability. Merced was a proof of concept. McKinley dramatically improved the memory hierarchy and allowed Itanium to become reasonably competitive. Madison, with the shift to a 130 nm process, allowed for enough cache space to overcome the major performance bottlenecks. Montecito, with a 90 nm process, allowed for a dual-core implementation and a major improvement in performance per watt. Montvale added three new features: core-level lockstep, demand-based switching and <a href="Front-side_bus" title="Front-side bus">front-side bus</a> frequency of up to 667 MHz.

<th><a href="List_of_Intel_codenames" title="List of Intel codenames">Codename</a></th>

<th>process</th>

<th>Released</th>

<th>Clock</th>

<th>L2 <a href="CPU_cache" title="CPU cache">Cache</a>/ core</th>

<th>L3 <a href="CPU_cache" title="CPU cache">Cache</a>/ processor</th>

<th>cores/ <a href="Die_(integrated_circuit)" title="Die (integrated circuit)">die</a></th>

<th>Comments

</th></tr>

<tr>

<th colspan="11" style="background:#ffebad;">Itanium

</th></tr>

<tr>

<td rowspan="2" style="vertical-align:top;">Merced</td>

<td rowspan="2">1 MB

2 MB

</td>

<td>2 or 4 MB off-die L3 cache

</td></tr>

<tr>

<td>2 or 4 MB off-die L3 cache

</td></tr>

<tr>

<th colspan="11" style="background:#ffebad;">Itanium 2

</th></tr>

<tr>

<td rowspan="3" style="vertical-align:top;">McKinley</td>

<td rowspan="3" style="vertical-align:top;">HW branchlong

</td></tr>

<tr>

<td style="border-style: solid solid none solid;">100

</td></tr>

<tr>

</td></tr>

<tr>

<td rowspan="6" style="vertical-align:top;">Madison</td>

<td>

</td></tr>

<tr>

<td>

</td></tr>

<tr>

<td>

</td></tr>

<tr>

<td>

</td></tr>

<tr>

<td>

</td></tr>

<tr>

<td>

</td></tr>

<tr>

<td>Deerfield</td>

<td>Low voltage

</td></tr>

<tr>

<td>Hondo<a href="#cite_note-221">[216]</a></td>

<td>Not a product of Intel, but of <a href="Hewlett-Packard" title="Hewlett-Packard">HP</a>. 32 MB L4

</td></tr>

<tr>

<td rowspan="3" style="vertical-align:top;">Fanwood</td>

<td>Low voltage

</td></tr>

<tr>

<td>

</td></tr>

<tr>

<td>

</td></tr>

<tr>

<td rowspan="5" style="vertical-align:top;">Madison 9M</td>

<td>

</td></tr>

<tr>

<td>

</td></tr>

<tr>

<td>

</td></tr>

<tr>

<td>

</td></tr>

<tr>

<td>

</td></tr>

<tr>

<th colspan="11" style="background:#ffebad;">Itanium 2 9000 series

</th></tr>

<tr>

<td style="vertical-align:top;"><a href="Montecito_(processor)" title="Montecito (processor)">Montecito</a></td>

<td style="vertical-align:top;">Virtualization, Multithread, no HW IA-32

</td></tr>

<tr>

<th colspan="11" style="background:#ffebad;">Itanium 9100 series

</th></tr>

<tr>

<td valign="top"><a href="Montvale_(processor)" class="mw-redirect" title="Montvale (processor)">Montvale</a></td>

<td valign="top">Core-level lockstep, demand-based switching

</td></tr>

<tr>

<th colspan="11" style="background:#ffebad;">Itanium 9300 series

</th></tr>

<tr>

<td valign="top"><a href="Tukwila_(processor)" title="Tukwila (processor)">Tukwila</a></td>

<td valign="top">A new point-to-point processor interconnect, the <a href="Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">QPI</a>, replacing the <a href="Front-side_bus" title="Front-side bus">FSB</a>. <a href="Turbo_Boost" class="mw-redirect" title="Turbo Boost">Turbo Boost</a>

</td></tr>

<tr>

<th colspan="11" style="background:#ffebad;">Itanium 9500 series

</th></tr>

<tr>

<td valign="top"><a href="Poulson_(processor)" class="mw-redirect" title="Poulson (processor)">Poulson</a></td>

<td valign="top">Doubled issue width (from 6 to 12 instructions per cycle), Instruction Replay technology, Dual-domain hyperthreading<a href="#cite_note-223">[218]</a><a href="#cite_note-poulson-the-future-of-itanium-servers-128">[124]</a><a href="#cite_note-224">[219]</a>

</td></tr>

<tr>

<th colspan="11" style="background:#ffebad;">Itanium 9700 series

</th></tr>

<tr>

<td valign="top"><a href="Kittson_(processor)" class="mw-redirect" title="Kittson (processor)">Kittson</a></td>

<td>No architectural improvements over Poulson, 5 % higher clock for the top model

</td></tr>

<tr>

<th>Codename</th>

<th>process</th>

<th>Released</th>

<th>Clock</th>

<th>L2 Cache/ core</th>

<th>L3 Cache/ processor</th>

<th>cores/ die</th>

<th>watts/ dev.</th>

<th>Comments

</th></tr>

<tr>

<th colspan="11"><a href="List_of_Intel_Itanium_processors" title="List of Intel Itanium processors">List of Intel Itanium processors</a>

</th></tr></tbody></table>

<div class="mw-heading mw-heading2"><h2 id="Market_reception">Market reception</h2></div>

<div class="mw-heading mw-heading3"><h3 id="High-end_server_market">High-end server market</h3></div>

When first released in 2001, Itanium's performance was disappointing compared to better-established <a href="RISC" class="mw-redirect" title="RISC">RISC</a> and <a href="Complex_instruction_set_computing" class="mw-redirect" title="Complex instruction set computing">CISC</a> processors.<a href="#cite_note-anand-60">[56]</a><a href="#cite_note-Venturebeat-61">[57]</a> Emulation to run existing x86 applications and operating systems was particularly poor, with one benchmark in 2001 reporting that it was equivalent at best to a 100 <a href="Hertz" title="Hertz">MHz</a> Pentium in this mode (1.1 <a href="Hertz" title="Hertz">GHz</a> Pentiums were on the market at that time).<a href="#cite_note-225">[220]</a>

Itanium failed to make significant inroads against <a href="IA-32" title="IA-32">IA-32</a> or RISC, and suffered further following the arrival of <a href="X86-64" title="X86-64">x86-64</a> systems which offered greater compatibility with older x86 applications.

In a 2009 article on the history of the processor — "How the Itanium Killed the Computer Industry" — journalist <a href="John_C._Dvorak" title="John C. Dvorak">John C. Dvorak</a> reported "This continues to be one of the great fiascos of the last 50 years".<a href="#cite_note-226">[221]</a> Tech columnist <a href="Ashlee_Vance" title="Ashlee Vance">Ashlee Vance</a> commented that the delays and underperformance "turned the product into a joke in the chip industry".<a href="#cite_note-vance_late-150">[146]</a> In an interview, <a href="Donald_Knuth" title="Donald Knuth">Donald Knuth</a> said "The Itanium approach...was supposed to be so terrific—until it turned out that the wished-for compilers were basically impossible to write."<a href="#cite_note-227">[222]</a>

Both <a href="Red_Hat" title="Red Hat">Red Hat</a> and <a href="Microsoft" title="Microsoft">Microsoft</a> announced plans to drop Itanium support in their operating systems due to lack of market interest;<a href="#cite_note-last_ms-228">[223]</a><a href="#cite_note-last_rhel-229">[224]</a> however, other <a href="Linux_distribution" title="Linux distribution">Linux distributions</a> such as <a href="Gentoo_Linux" title="Gentoo Linux">Gentoo</a> and <a href="Debian" title="Debian">Debian</a> remain available for Itanium. On March 22, 2011, <a href="Oracle_Corporation" title="Oracle Corporation">Oracle Corporation</a> announced that it would no longer develop new products for HP-UX on Itanium, although it would continue to provide support for existing products.<a href="#cite_note-pcworld2011-230">[225]</a> Following this announcement, HP sued Oracle for breach of contract, arguing that Oracle had violated conditions imposed during settlement over Oracle's hiring of former HP CEO <a href="Mark_Hurd" title="Mark Hurd">Mark Hurd</a> as its co-CEO, requiring the vendor to support Itanium on its software "until such time as HP discontinues the sales of its Itanium-based servers",<a href="#cite_note-ars-oraclelawsuitwin-231">[226]</a> and that the breach had harmed its business. In 2012, a court ruled in favor of HP, and ordered Oracle to resume its support for Itanium. In June 2016, <a href="Hewlett_Packard_Enterprise" title="Hewlett Packard Enterprise">Hewlett Packard Enterprise</a> (the corporate successor to HP's server business) was awarded $3 billion in damages from the lawsuit.<a href="#cite_note-ars-itaniumlawsuit-232">[227]</a><a href="#cite_note-bloomberg-itanium3b-233">[228]</a> Oracle unsuccessfully appealed the decision to the California Court of Appeal in 2021.<a href="#cite_note-reuters-oracle-234">[229]</a>

A former Intel official reported that the Itanium business had become profitable for Intel in late 2009.<a href="#cite_note-235">[230]</a> By 2009, the chip was almost entirely deployed on servers made by HP, which had over 95% of the Itanium server market share,<a href="#cite_note-vance_late-150">[146]</a> making the main operating system for Itanium <a href="HP-UX" title="HP-UX">HP-UX</a>. On March 22, 2011, Intel reaffirmed its commitment to Itanium with multiple generations of chips in development and on schedule.<a href="#cite_note-Intel_Itanium_Commitment-236">[231]</a>

<div class="mw-heading mw-heading3"><h3 id="Other_markets">Other markets</h3></div>

Although Itanium did attain limited success in the niche market of high-end computing, Intel had originally hoped it would find broader acceptance as a replacement for the original <a href="X86" title="X86">x86</a> architecture.<a href="#cite_note-237">[232]</a>

<a href="AMD" title="AMD">AMD</a> chose a different direction, designing the less radical <a href="X86-64" title="X86-64">x86-64</a>, a 64-bit extension to the existing x86 architecture, which Microsoft then supported, forcing Intel to introduce the same extensions in its own x86-based processors.<a href="#cite_note-238">[233]</a> These designs can run existing 32-bit applications at native hardware speed, while offering support for 64-bit memory addressing and other enhancements to new applications.<a href="#cite_note-vance_late-150">[146]</a> This architecture has now become the predominant 64-bit architecture in the desktop and portable market. Although some Itanium-based workstations were initially introduced by companies such as <a href="Silicon_Graphics" title="Silicon Graphics">SGI</a>, they are no longer available.

<ul><li><a href="List_of_Intel_Itanium_processors" title="List of Intel Itanium processors">List of Intel Itanium processors</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2></div>

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<li id="cite_note-6"><a href="#cite_ref-6">^</a> Itanium was launched on 29 May,<a href="#cite_note-2">[2]</a><a href="#cite_note-3">[3]</a><a href="#cite_note-4">[4]</a><a href="#cite_note-5">[5]</a> but the computers containing it shipped to customers in June.

</li>

<li id="cite_note-7"><a href="#cite_ref-7">^</a> Hondo is an HP product, not an Intel product

</li>

<li id="cite_note-16"><a href="#cite_ref-16">^</a> The size of the needed dependency-checking circuitry increases <a href="Quadratic_growth" title="Quadratic growth">quadratically</a> with the issue width.<a href="#cite_note-simplicity-14">[12]</a><a href="#cite_note-Understanding_EPIC-15">[13]</a>

</li>

<li id="cite_note-35"><a href="#cite_ref-35">^</a> For comparison the 180nm Pentium III Xeon MP had a 2 MB on-die L2 cache.

</li>

<li id="cite_note-156"><a href="#cite_ref-156">^</a> the processor supported TAP (<a href="JTAG" title="JTAG">JTAG</a>) and <a href="SMBus" class="mw-redirect" title="SMBus">SMBus</a> for debugging and system configuration

</li>

</ol></div></div>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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/* end https://en.wikipedia.org/ */

</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://qdms.intel.com/dm/i.aspx/F65EEA26-13FB-4580-972B-46B75E0AB322/PCN116733-00.pdf">"Select Intel Itanium Processors and Intel Scalable Memory Buffer, PCN 116733-00, Product Discontinuance, End of Life"</a> (PDF). Intel. January 30, 2019. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200522180927/https://qdms.intel.com/dm/i.aspx/F65EEA26-13FB-4580-972B-46B75E0AB322/PCN116733-00.pdf">Archived</a> (PDF) from the original on May 22, 2020. Retrieved May 20, 2020.</cite> (January 30, 2020 was the last date for placing an order, all shipped no later than July 29, 2021).

</li>

<li id="cite_note-2"><a href="#cite_ref-2">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.computerworld.com/article/2582076/intel-officially-launches-64-bit-itanium-chip.html">"Intel officially launches 64-bit Itanium chip"</a>. <a href="Computerworld" title="Computerworld">Computerworld</a>. 29 May 2001.</cite>

</li>

<li id="cite_note-3"><a href="#cite_ref-3">^</a> <cite id="CITEREFFordahl2001" class="citation web cs1">Fordahl, Matthew (30 May 2001). <a rel="nofollow" class="external text" href="https://abcnews.go.com/Technology/story?id=98536&page=1">"Intel, HP Launch New Processor"</a>. <a href="ABC_News_(United_States)" title="ABC News (United States)">ABC News</a>.</cite>

</li>

<li id="cite_note-4"><a href="#cite_ref-4">^</a> <cite id="CITEREFBekker2001" class="citation web cs1">Bekker, Scott (29 May 2001). <a rel="nofollow" class="external text" href="https://rcpmag.com/articles/2001/05/29/intel-launches-itanium-oems-unveil-systems.aspx">"Intel Launches Itanium: OEMs Unveil Systems"</a>. RCP Mag.</cite>

</li>

<li id="cite_note-5"><a href="#cite_ref-5">^</a> <cite id="CITEREFKerridge2001" class="citation web cs1">Kerridge, Suzanna (18 May 2001). <a rel="nofollow" class="external text" href="https://www.zdnet.com/article/intel-opens-up-about-forthcoming-itanium-family/">"Intel opens up about forthcoming Itanium family"</a>. <a href="ZDNet" class="mw-redirect" title="ZDNet">ZDNet</a>.</cite>

</li>

<li id="cite_note-ITJungle-8"><a href="#cite_ref-ITJungle_8-0">^</a> <cite id="CITEREFMorgan2008" class="citation web cs1">Morgan, Timothy (May 27, 2008). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160303203839/http://www.itjungle.com/tlb/tlb052708-story03.html">"The Server Biz Enjoys the X64 Upgrade Cycle in Q1"</a>. IT Jungle. Archived from <a rel="nofollow" class="external text" href="http://www.itjungle.com/tlb/tlb052708-story03.html">the original</a> on March 3, 2016. Retrieved October 29, 2008.</cite>

</li>

<li id="cite_note-Davis_2017-9">^ <a href="#cite_ref-Davis_2017_9-0">a</a> <a href="#cite_ref-Davis_2017_9-1">b</a> <cite id="CITEREFDavis2017" class="citation web cs1">Davis, Lisa M. (May 11, 2017). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180908094221/https://itpeernetwork.intel.com/evolution-mission-critical-computing/">"The Evolution of Mission Critical Computing"</a>. Intel. Archived from <a rel="nofollow" class="external text" href="https://itpeernetwork.intel.com/evolution-mission-critical-computing/">the original</a> on September 8, 2018. Retrieved May 11, 2017. <q>...the 9700 series will be the last Intel Itanium processor.</q></cite>

</li>

<li id="cite_note-IA-PCWorld-10">^ <a href="#cite_ref-IA-PCWorld_10-0">a</a> <a href="#cite_ref-IA-PCWorld_10-1">b</a> <a href="#cite_ref-IA-PCWorld_10-2">c</a> <a href="#cite_ref-IA-PCWorld_10-3">d</a> <cite id="CITEREFShah2017" class="citation web cs1">Shah, Agam (May 11, 2017). <a rel="nofollow" class="external text" href="https://www.pcworld.com/article/3196080/intels-itanium-once-destined-to-replace-x86-in-pcs-hits-end-of-line.html">"Intel's Itanium, once destined to replace x86 processors in PCs, hits end of line"</a>. <a href="PC_World" title="PC World">PC World</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190315153959/https://www.pcworld.com/article/3196080/intels-itanium-once-destined-to-replace-x86-in-pcs-hits-end-of-line.html">Archived</a> from the original on March 15, 2019. Retrieved May 20, 2020.</cite>

</li>

<li id="cite_note-EoL-11"><a href="#cite_ref-EoL_11-0">^</a> <cite id="CITEREFSharwood2021" class="citation news cs1">Sharwood, Simon (July 30, 2021). <a rel="nofollow" class="external text" href="https://www.theregister.com/2021/07/30/end_of_itanium_shipments/">"The Register just found 300-odd Itanium CPUs on eBay"</a>. <a href="The_Register" title="The Register">The Register</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20210912101014/https://www.theregister.com/2021/07/30/end_of_itanium_shipments/">Archived</a> from the original on September 12, 2021. Retrieved September 12, 2021.</cite>

</li>

<li id="cite_note-Gartner_2009-q4-12">^ <a href="#cite_ref-Gartner_2009-q4_12-0">a</a> <a href="#cite_ref-Gartner_2009-q4_12-1">b</a> <a href="#cite_ref-Gartner_2009-q4_12-2">c</a> <cite id="CITEREFMorgan2010" class="citation news cs1">Morgan, Timothy Prickett (February 24, 2010). <a rel="nofollow" class="external text" href="https://www.theregister.com/2010/02/24/gartner_q4_2009_servers/">"Gartner report card gives high marks to x64, blades"</a>. <a href="The_Register" title="The Register">The Register</a>. Retrieved November 25, 2022.</cite>

</li>

<li id="cite_note-13"><a href="#cite_ref-13">^</a> <cite id="CITEREFLee2021" class="citation web cs1">Lee, Matthew (August 2021). <a rel="nofollow" class="external text" href="https://www.techspot.com/news/90622-intel-itanium-finally-dead.html">"Intel's Itanium is finally dead: The Itanic sunken by the x86 juggernaut"</a>. Techspot. Retrieved 26 March 2023.</cite>

</li>

<li id="cite_note-simplicity-14">^ <a href="#cite_ref-simplicity_14-0">a</a> <a href="#cite_ref-simplicity_14-1">b</a> <cite id="CITEREFDeMone1999" class="citation web cs1">DeMone, Paul (27 October 1999). <a rel="nofollow" class="external text" href="https://www.realworldtech.com/hp-intel-itanium/">"HP's Struggle For Simplicity Ends at Intel"</a>. Real World Tech.</cite>

</li>

<li id="cite_note-Understanding_EPIC-15">^ <a href="#cite_ref-Understanding_EPIC_15-0">a</a> <a href="#cite_ref-Understanding_EPIC_15-1">b</a> <cite id="CITEREFSmotherman" class="citation web cs1">Smotherman, Mark. <a rel="nofollow" class="external text" href="https://people.computing.clemson.edu/~mark/464/acmse_epic.pdf">"Understanding EPIC Architectures and Implementations"</a> (PDF). <a href="Clemson_University" title="Clemson University">Clemson University</a>. Retrieved 5 June 2022.</cite>

</li>

<li id="cite_note-HP_Labs-17">^ <a href="#cite_ref-HP_Labs_17-0">a</a> <a href="#cite_ref-HP_Labs_17-1">b</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.hpl.hp.com/news/2001/apr-jun/itanium.html">"Inventing Itanium: How HP Labs Helped Create the Next-Generation Chip Architecture"</a>. <a href="HP_Labs" title="HP Labs">HP Labs</a>. June 2001. Retrieved March 23, 2007.</cite>

</li>

<li id="cite_note-nyt_merced-18">^ <a href="#cite_ref-nyt_merced_18-0">a</a> <a href="#cite_ref-nyt_merced_18-1">b</a> <a href="#cite_ref-nyt_merced_18-2">c</a> <a href="#cite_ref-nyt_merced_18-3">d</a> <cite id="CITEREFMarkoff1998" class="citation web cs1">Markoff, John (5 April 1998). <a rel="nofollow" class="external text" href="https://archive.org/details/TheJerusalemPost1998IsraelEnglish/Apr%2006%201998%2C%20The%20Jerusalem%20Post%2C%20%2319898%2C%20Israel%20%28en%29/page/n12/mode/1up">"Inside Intel, The Future is Riding on the Merced Chip"</a>. <a href="The_New_York_Times" title="The New York Times">The New York Times</a>, republised by <a href="The_Jerusalem_Post" title="The Jerusalem Post">The Jerusalem Post</a>.</cite>

</li>

<li id="cite_note-19"><a href="#cite_ref-19">^</a> <cite id="CITEREFDeMone2000" class="citation web cs1">DeMone, Paul (25 January 2000). <a rel="nofollow" class="external text" href="https://www.realworldtech.com/intel-history-lesson/">"Intel's History Lesson"</a>. Real World Tech.</cite>

</li>

<li id="cite_note-countdown-20">^ <a href="#cite_ref-countdown_20-0">a</a> <a href="#cite_ref-countdown_20-1">b</a> <cite id="CITEREFDeMone2001" class="citation web cs1">DeMone, Paul (14 March 2001). <a rel="nofollow" class="external text" href="https://www.realworldtech.com/countdown-to-ia64/">"Countdown to IA-64"</a>. Real World Tech.</cite>

</li>

<li id="cite_note-21"><a href="#cite_ref-21">^</a> <cite id="CITEREFSmotherman" class="citation web cs1">Smotherman, Mark. <a rel="nofollow" class="external text" href="https://people.computing.clemson.edu/~mark/architects.html">"Who are the Computer Architects?"</a>. <a href="Clemson_University" title="Clemson University">Clemson University</a>.</cite> See the sections "Independence architecture" and "Wintel".

</li>

<li id="cite_note-22"><a href="#cite_ref-22">^</a> <cite id="CITEREFAlpert2003" class="citation web cs1">Alpert, Donald (July 2003). <a rel="nofollow" class="external text" href="https://camelback-comparch.com/about/technical-highlights/#merced">"Intel Itanium Processor (Merced)"</a>.</cite> Alpert was the chief architect of the original P7 and the top engineering manager of Merced<a href="#cite_note-21">[18]</a>

</li>

<li id="cite_note-23"><a href="#cite_ref-23">^</a> <cite id="CITEREFDeMone2000" class="citation web cs1">DeMone, Paul (3 March 2000). <a rel="nofollow" class="external text" href="https://www.realworldtech.com/willamette-basics/">"What's Up With Willamette? (Part 1)"</a>. Real World Tech.</cite>

</li>

<li id="cite_note-24"><a href="#cite_ref-24">^</a> <cite id="CITEREFKanellos2003" class="citation web cs1">Kanellos, Michael (21 February 2003). <a rel="nofollow" class="external text" href="https://www.cnet.com/tech/tech-industry/intel-takes-slow-road-to-64-bit-pc-chips/">"Intel takes slow road to 64-bit PC chips"</a>. <a href="CNET" title="CNET">CNET</a>.</cite>

</li>

<li id="cite_note-gambles-25">^ <a href="#cite_ref-gambles_25-0">a</a> <a href="#cite_ref-gambles_25-1">b</a> <a href="#cite_ref-gambles_25-2">c</a> <cite id="CITEREFHamilton2001" class="citation web cs1">Hamilton, David (28 May 2001). <a rel="nofollow" class="external text" href="https://www.zdnet.com/article/intel-gambles-with-itanium/">"Intel gambles with Itanium"</a>. <a href="ZDNet" class="mw-redirect" title="ZDNet">ZDNet</a>.</cite>

</li>

<li id="cite_note-birth-26"><a href="#cite_ref-birth_26-0">^</a> <cite id="CITEREFBritt2000" class="citation web cs1">Britt, Russ (1 January 2000). <a rel="nofollow" class="external text" href="https://www.edn.com/the-birth-of-a-new-processor/">"The birth of a new processor"</a>. <a href="EDN_(magazine)" title="EDN (magazine)">EDN</a>.</cite>

</li>

<li id="cite_note-27"><a href="#cite_ref-27">^</a> <cite id="CITEREFSmotherman" class="citation web cs1">Smotherman, Mark. <a rel="nofollow" class="external text" href="https://people.computing.clemson.edu/~mark/epic.html">"Historical background for EPIC instruction set architectures"</a>. <a href="Clemson_University" title="Clemson University">Clemson University</a>. Retrieved 3 June 2022.</cite>

</li>

<li id="cite_note-28"><a href="#cite_ref-28">^</a> <a href="#cite_note-countdown-20">[17]</a><a href="#cite_note-birth-26">[23]</a> (The <abbr title="architecture, compilers, microarchitecture">ACM</abbr> committee with 5 people from each side<a href="#cite_note-27">[24]</a> was probably a different entity.)

</li>

<li id="cite_note-29"><a href="#cite_ref-29">^</a> <cite id="CITEREFKathailSchlanskerRau" class="citation web cs1">Kathail, Vinod; Schlansker, Michael S.; Rau, B. Ramakrishna. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240204063521/https://www.hpl.hp.com/techreports/93/HPL-93-80R1.pdf">"HPL-PD Architecture Specification: Version 1.1"</a> (PDF). <a href="HP_Labs" title="HP Labs">HP Laboratories</a>. Archived from <a rel="nofollow" class="external text" href="https://www.hpl.hp.com/techreports/93/HPL-93-80R1.pdf">the original</a> (PDF) on 2024-02-04. Retrieved 2023-07-05.</cite>

</li>

<li id="cite_note-30"><a href="#cite_ref-30">^</a> <cite id="CITEREFHecht1994" class="citation web cs1">Hecht, Jeff (18 June 1994). <a rel="nofollow" class="external text" href="https://www.newscientist.com/article/mg14219303-300-technology-intel-opts-for-simpler-speedier-chips/">"Technology: Intel opts for simpler, speedier chips"</a>. <a href="New_Scientist" title="New Scientist">New Scientist</a>.</cite>

</li>

<li id="cite_note-31"><a href="#cite_ref-31">^</a> <cite id="CITEREFBozman1994" class="citation web cs1">Bozman, Jean S. (13 June 1994). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=QZtKFFB8weQC&pg=PA12">"Chip alliance shakes ground"</a>. <a href="Computerworld" title="Computerworld">Computerworld</a>.</cite> David House had approved the project, but later severely criticized it.

</li>

<li id="cite_note-32"><a href="#cite_ref-32">^</a> <cite id="CITEREFBabcock1994" class="citation web cs1">Babcock, Charles (25 July 1994). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=QtpyKsPTNwkC&pg=PA6">"Silicon marriage: HP/Intel venture"</a>. <a href="Computerworld" title="Computerworld">Computerworld</a>.</cite>

</li>

<li id="cite_note-33"><a href="#cite_ref-33">^</a> <cite id="CITEREFDeMone2001" class="citation web cs1">DeMone, Paul (14 March 2001). <a rel="nofollow" class="external text" href="https://www.realworldtech.com/countdown-to-ia64/">"Countdown to IA-64"</a>. Real World Tech.</cite> Has a typo (P5) in the graphic.

</li>

<li id="cite_note-34"><a href="#cite_ref-34">^</a> <cite id="CITEREFCrothers1996" class="citation web cs1">Crothers, Brooke (29 January 1996). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=zD4EAAAAMBAJ&pg=PA8">"Intel aims to bring multimedia to the masses"</a>. <a href="InfoWorld" title="InfoWorld">InfoWorld</a>.</cite>

</li>

<li id="cite_note-36"><a href="#cite_ref-36">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://techmonitor.ai/technology/merced_will_be_out_late_1999_says_hewlett_packard_1">"Merced "Will Be Out Late 1999," Says Hewlett-Packard"</a>. Tech Monitor. Computer Business Review. 18 July 1997. <a rel="nofollow" class="external text" href="https://archive.today/20240213040233/https://techmonitor.ai/technology/merced_will_be_out_late_1999_says_hewlett_packard_1">Archived</a> from the original on 13 February 2024.</cite>

</li>

<li id="cite_note-37"><a href="#cite_ref-37">^</a> <cite id="CITEREFKanellos1997" class="citation web cs1">Kanellos, Michael (6 October 1997). <a rel="nofollow" class="external text" href="https://www.cnet.com/news/intel-late-to-64-bit-computing/">"Intel late to 64-bit computing"</a>. <a href="CNET" title="CNET">CNET</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220627172827/https://www.cnet.com/tech/tech-industry/intel-late-to-64-bit-computing/">Archived</a> from the original on Jun 27, 2022.</cite>

</li>

<li id="cite_note-cnet_unveil_epic-38">^ <a href="#cite_ref-cnet_unveil_epic_38-0">a</a> <a href="#cite_ref-cnet_unveil_epic_38-1">b</a> <cite id="CITEREFKanellos1997" class="citation web cs1">Kanellos, Michael (14 October 1997). <a rel="nofollow" class="external text" href="https://www.cnet.com/news/intel-hp-unveil-epic-technology/">"Intel, HP unveil EPIC technology"</a>. <a href="CNET" title="CNET">CNET</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220818183735/https://www.cnet.com/tech/tech-industry/intel-hp-unveil-epic-technology/">Archived</a> from the original on Aug 18, 2022.</cite>

</li>

<li id="cite_note-39"><a href="#cite_ref-39">^</a> <cite id="CITEREFDeMone1999" class="citation web cs1">DeMone, Paul (27 October 1999). <a rel="nofollow" class="external text" href="https://www.realworldtech.com/hp-intel-itanium/3/">"HP's Struggle For Simplicity Ends at Intel"</a>. Real World Tech. p. 3. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231031163355/https://www.realworldtech.com/hp-intel-itanium/3/">Archived</a> from the original on Oct 31, 2023.</cite>

</li>

<li id="cite_note-40"><a href="#cite_ref-40">^</a> <cite id="CITEREFGwennap1997" class="citation news cs1">Gwennap, Linley (27 October 1997). <a rel="nofollow" class="external text" href="https://www.cs.virginia.edu/~skadron/cs854_uproc_survey/spring_2001/cs854/111401.pdf">"Intel, HP Make EPIC Disclosure"</a> (PDF). <a href="Microprocessor_Report" title="Microprocessor Report">Microprocessor Report</a>. Vol. 11, no. 14. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231031163335/https://www.cs.virginia.edu/~skadron/cs854_uproc_survey/spring_2001/cs854/111401.pdf">Archived</a> (PDF) from the original on Oct 31, 2023.</cite>

</li>

<li id="cite_note-41"><a href="#cite_ref-41">^</a> <cite id="CITEREFCorcoran1997" class="citation news cs1">Corcoran, Elizabeth (15 October 1997). <a rel="nofollow" class="external text" href="https://www.washingtonpost.com/archive/business/1997/10/15/chipmakers-unveil-works-in-progress/b4ecf2c5-7c6b-419e-a0d1-9c35d515b5e0/">"Chipmakers unveil works in progress"</a>. <a href="The_Washington_Post" title="The Washington Post">The Washington Post</a>. <a rel="nofollow" class="external text" href="https://archive.today/20240213044222/https://www.washingtonpost.com/archive/business/1997/10/15/chipmakers-unveil-works-in-progress/b4ecf2c5-7c6b-419e-a0d1-9c35d515b5e0/">Archived</a> from the original on 13 February 2024.</cite>

</li>

<li id="cite_note-zdnet_wait-42">^ <a href="#cite_ref-zdnet_wait_42-0">a</a> <a href="#cite_ref-zdnet_wait_42-1">b</a> <cite id="CITEREFRobertson1999" class="citation web cs1">Robertson, Chiyo (17 March 1999). <a rel="nofollow" class="external text" href="https://www.zdnet.com/article/merced-worth-the-wait-what-of-mckinley/">"Merced: Worth the wait? What of McKinley?"</a>. <a href="ZDNet" class="mw-redirect" title="ZDNet">ZDNet</a>.</cite>

</li>

<li id="cite_note-43"><a href="#cite_ref-43">^</a> <cite id="CITEREFMatsumoto1998" class="citation web cs1">Matsumoto, Craig (8 October 1998). <a rel="nofollow" class="external text" href="https://www.eetimes.com/intel-outlines-road-to-mckinley-processor/">"Intel outlines road to McKinley processor"</a>. <a href="EE_Times" title="EE Times">EE Times</a>.</cite>

</li>

<li id="cite_note-HP_McKinley_wp-44">^ <a href="#cite_ref-HP_McKinley_wp_44-0">a</a> <a href="#cite_ref-HP_McKinley_wp_44-1">b</a> <cite class="citation citeseerx cs1">"Inside the Intel Itanium 2 Processor: a Hewlett Packard Technical White Paper". 17 July 2002. <a href="CiteSeerX_(identifier)" class="mw-redirect" title="CiteSeerX (identifier)">CiteSeerX</a> <a rel="nofollow" class="external text" href="https://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.96.8209">10.1.1.96.8209</a>.</cite>

</li>

<li id="cite_note-45"><a href="#cite_ref-45">^</a> <cite id="CITEREFKanellos1998" class="citation web cs1">Kanellos, Michael (6 August 1998). <a rel="nofollow" class="external text" href="https://www.cnet.com/tech/tech-industry/is-merced-doomed/">"Is Merced doomed?"</a>. <a href="CNET" title="CNET">CNET</a>.</cite>

</li>

<li id="cite_note-46"><a href="#cite_ref-46">^</a> <cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://techmonitor.ai/technology/intels_merced_could_be_eclipsed_by_mckinley_follow_on">"INTEL'S MERCED COULD BE ECLIPSED BY MCKINLEY FOLLOW-ON"</a>. Tech Monitor. 6 August 1998.</cite>

</li>

<li id="cite_note-47"><a href="#cite_ref-47">^</a> <cite id="CITEREFShanklandKanellos1998" class="citation web cs1">Shankland, Stephen; Kanellos, Michael (13 October 1998). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20001203183700/http://cnet.com/news/0-1004-200-334214.html">"HP has two-pronged chip plan"</a>. <a href="CNET" title="CNET">CNET</a>. Archived from <a rel="nofollow" class="external text" href="http://cnet.com/news/0-1004-200-334214.html">the original</a> on 2000-12-03.</cite>

</li>

<li id="cite_note-48"><a href="#cite_ref-48">^</a> <cite id="CITEREFGary1999" class="citation web cs1">Gary, Gregory (3 May 1999). <a rel="nofollow" class="external text" href="https://www.edn.com/ia-64-update-part-1-of-2/">"IA 64 Update: Part 1 of 2"</a>. <a href="EDN_(magazine)" title="EDN (magazine)">EDN</a>.</cite>

</li>

<li id="cite_note-may_slip-49">^ <a href="#cite_ref-may_slip_49-0">a</a> <a href="#cite_ref-may_slip_49-1">b</a> <cite id="CITEREFShankland1999" class="citation web cs1">Shankland, Stephen (8 July 1999). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20000605083119/http://news.cnet.com/news/0-1003-200-344601.html">"Intel's Merced chip may slip further"</a>. <a href="CNET" title="CNET">CNET</a>. Archived from <a rel="nofollow" class="external text" href="http://news.cnet.com/news/0-1003-200-344601.html">the original</a> on 2000-06-05.</cite>

</li>

<li id="cite_note-50"><a href="#cite_ref-50">^</a> <cite id="CITEREFHamblen1999" class="citation web cs1">Hamblen, Matt (12 July 1999). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=51iIcvzoX-AC&pg=PA61">"Intel: No Forced March to Merced"</a>. <a href="Computerworld" title="Computerworld">Computerworld</a>.</cite>

</li>

<li id="cite_note-51"><a href="#cite_ref-51">^</a> <cite id="CITEREFShankland1999" class="citation web cs1">Shankland, Stephen (19 August 1999). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20000819022147/http://news.cnet.com/news/0-1003-200-346220.html">"HP upgrade path bypasses Merced chip"</a>. <a href="CNET" title="CNET">CNET</a>. Archived from <a rel="nofollow" class="external text" href="http://news.cnet.com/news/0-1003-200-346220.html">the original</a> on 2000-08-19.</cite>

</li>

<li id="cite_note-52"><a href="#cite_ref-52">^</a> <cite id="CITEREFShankland2000" class="citation web cs1">Shankland, Stephen (11 July 2000). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20010210011931/http://www.news.cnet.com/news/0-1003-200-2241414.html">"HP moves slowly into world of Intel 64-bit processors"</a>. <a href="CNET" title="CNET">CNET</a>. Archived from <a rel="nofollow" class="external text" href="http://www.news.cnet.com/news/0-1003-200-2241414.html">the original</a> on 2001-02-10.</cite>

</li>

<li id="cite_note-53"><a href="#cite_ref-53">^</a> <cite id="CITEREFShanklandKanellos2000" class="citation web cs1">Shankland, Stephen; Kanellos, Michael (July 18, 2000). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20010413122744/http://news.cnet.com/news/0-1003-200-2284759.html">"Intel pushes back schedule for Itanium chip"</a>. <a href="CNET" title="CNET">CNET</a>. Archived from <a rel="nofollow" class="external text" href="http://news.cnet.com/news/0-1003-200-2284759.html">the original</a> on 2001-04-13.</cite>

</li>

<li id="cite_note-54"><a href="#cite_ref-54">^</a> <cite id="CITEREFShankland2001" class="citation web cs1">Shankland, Stephen (1 March 2001). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20010413151817/http://news.cnet.com/news/0-1003-200-4996738.html">"Intel draws out Itanium arrival"</a>. <a href="CNET" title="CNET">CNET</a>. Archived from <a rel="nofollow" class="external text" href="http://news.cnet.com/news/0-1003-200-4996738.html">the original</a> on 2001-04-13.</cite>

</li>

<li id="cite_note-IDC_chart-55"><a href="#cite_ref-IDC_chart_55-0">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20180611040452/https://www.zdnet.com/pictures/charts-mining-itanium/">"Mining Itanium"</a>. CNet News. December 7, 2005. Archived from <a rel="nofollow" class="external text" href="https://www.zdnet.com/pictures/charts-mining-itanium/">the original</a> on June 11, 2018. Retrieved March 19, 2007.</cite>

</li>

<li id="cite_note-IDC_2006-56"><a href="#cite_ref-IDC_2006_56-0">^</a> <cite id="CITEREFShankland2006" class="citation news cs1">Shankland, Stephen (February 14, 2006). <a rel="nofollow" class="external text" href="https://www.cnet.com/news/analyst-firm-offers-rosy-view-of-itanium/">"Analyst firm offers rosy view of Itanium"</a>. <a href="CNET" title="CNET">CNET News</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160624090721/http://www.cnet.com/news/analyst-firm-offers-rosy-view-of-itanium/">Archived</a> from the original on June 24, 2016. Retrieved March 20, 2007.</cite>

</li>

<li id="cite_note-57"><a href="#cite_ref-57">^</a> <cite id="CITEREFHalfhill1997" class="citation web cs1">Halfhill, Tom R. (December 1997). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20000302143120/http://www.byte.com/art/9712/sec5/art1.htm">"Beyond Pentium II"</a>. <a href="Byte_(magazine)" title="Byte (magazine)">Byte</a>. Archived from <a rel="nofollow" class="external text" href="http://www.byte.com/art/9712/sec5/art1.htm">the original</a> on 2000-03-02.</cite>

</li>

<li id="cite_note-58"><a href="#cite_ref-58">^</a> <cite id="CITEREFConnor1999" class="citation web cs1">Connor, Deni (1 March 1999). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=AxwEAAAAMBAJ&pg=PA61">"Intel's Merced will coexist with 32-bit chips"</a>. <a href="Network_World" class="mw-redirect" title="Network World">Network World</a>.</cite>

</li>

<li id="cite_note-59"><a href="#cite_ref-59">^</a> <cite id="CITEREFKnorr2001" class="citation web cs1">Knorr, Eric (10 September 2001). <a rel="nofollow" class="external text" href="https://www.zdnet.com/article/upgrading-your-server-a-look-at-the-itanium/">"Upgrading your server: A look at the Itanium"</a>. <a href="ZDNet" class="mw-redirect" title="ZDNet">ZDNet</a>.</cite>

</li>

<li id="cite_note-anand-60">^ <a href="#cite_ref-anand_60-0">a</a> <a href="#cite_ref-anand_60-1">b</a> <cite id="CITEREFDe_Gelas2005" class="citation web cs1">De Gelas, Johan (November 9, 2005). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120503094946/http://www.anandtech.com/show/1854">"Itanium–Is there light at the end of the tunnel?"</a>. <a href="AnandTech" title="AnandTech">AnandTech</a>. Archived from <a rel="nofollow" class="external text" href="http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2598">the original</a> on May 3, 2012. Retrieved March 23, 2007.</cite>

</li>

<li id="cite_note-Venturebeat-61">^ <a href="#cite_ref-Venturebeat_61-0">a</a> <a href="#cite_ref-Venturebeat_61-1">b</a> <cite id="CITEREFTakahashi2009" class="citation web cs1">Takahashi, Dean (May 8, 2009). <a rel="nofollow" class="external text" href="https://venturebeat.com/2009/05/08/exit-interview-retiring-intel-chairman-craig-barrett-on-the-industrys-unfinished-business/">"Exit interview: Retiring Intel chairman Craig Barrett on the industry's unfinished business"</a>. VentureBeat. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180421095016/https://venturebeat.com/2009/05/08/exit-interview-retiring-intel-chairman-craig-barrett-on-the-industrys-unfinished-business/">Archived</a> from the original on April 21, 2018. Retrieved May 17, 2009.</cite>

</li>

<li id="cite_note-62"><a href="#cite_ref-62">^</a> <cite id="CITEREFNash1998" class="citation web cs1">Nash, Kim S. (6 July 1998). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=03nTlQZ61IgC&pg=PT14">"Behind the Merced Mystique"</a>. <a href="Computerworld" title="Computerworld">Computerworld</a>.</cite>

</li>

<li id="cite_note-63"><a href="#cite_ref-63">^</a> <cite id="CITEREFYu1998" class="citation web cs1">Yu, Elleen (25 November 1998). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230129171855/https://www.arnnet.com.au/article/110877/ia-64_overtake_risc/">"IA-64 to overtake RISC"</a>. ARN. Archived from <a rel="nofollow" class="external text" href="https://www.arnnet.com.au/article/110877/ia-64_overtake_risc/">the original</a> on 29 January 2023. Retrieved 16 August 2022.</cite>

</li>

<li id="cite_note-cautionary-64">^ <a href="#cite_ref-cautionary_64-0">a</a> <a href="#cite_ref-cautionary_64-1">b</a> <a href="#cite_ref-cautionary_64-2">c</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.zdnet.com/article/itanium-a-cautionary-tale/">"Itanium: A cautionary tale"</a>. Tech News on ZDNet. December 7, 2005. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200802000433/https://www.zdnet.com/article/itanium-a-cautionary-tale/">Archived</a> from the original on August 2, 2020. Retrieved January 1, 2019.</cite>

</li>

<li id="cite_note-Solaris-Merced1-65"><a href="#cite_ref-Solaris-Merced1_65-0">^</a> <cite id="CITEREFVijayan1999" class="citation web cs1">Vijayan, Jaikumar (September 1, 1999). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20000115084746/http://www.computerworld.com/home/news.nsf/all/9909013sunsol">"Solaris for IA-64 coming this fall"</a>. <a href="Computerworld" title="Computerworld">Computerworld</a>. Archived from <a rel="nofollow" class="external text" href="http://www.computerworld.com/home/news.nsf/all/9909013sunsol">the original</a> on January 15, 2000.</cite>

</li>

<li id="cite_note-Solaris-Merced2-66"><a href="#cite_ref-Solaris-Merced2_66-0">^</a> <cite id="CITEREFWolfe1999" class="citation news cs1">Wolfe, Alexander (September 2, 1999). <a rel="nofollow" class="external text" href="https://www.eetimes.com/core-logic-efforts-under-way-for-merced/">"Core-logic efforts under way for Merced"</a>. <a href="EE_Times" title="EE Times">EE Times</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20191217201650/https://www.eetimes.com/core-logic-efforts-under-way-for-merced/">Archived</a> from the original on December 17, 2019. Retrieved December 17, 2019.</cite>

</li>

<li id="cite_note-Solaris-Merced3-67"><a href="#cite_ref-Solaris-Merced3_67-0">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20160805145446/http://www.thefreelibrary.com/Sun+Introduces+Solaris+Developer+Kit+for+Intel+to+Speed+Development...-a020369933">"Sun Introduces Solaris Developer Kit for Intel to Speed Development of Applications On Solaris; Award-winning Sun Tools Help ISVs Easily Develop for Solaris on Intel Today"</a>. Business Wire. March 10, 1998. Archived from <a rel="nofollow" class="external text" href="http://www.thefreelibrary.com/Sun+Introduces+Solaris+Developer+Kit+for+Intel+to+Speed+Development...-a020369933">the original</a> on August 5, 2016. Retrieved June 6, 2016. <q>...developers can quickly develop applications today that will be compatible with and can easily be tuned for Solaris on Merced.</q></cite>

</li>

<li id="cite_note-68"><a href="#cite_ref-68">^</a> <cite id="CITEREFShankland1999" class="citation news cs1">Shankland, Stephen (September 17, 1999). <a rel="nofollow" class="external text" href="https://www.cnet.com/tech/tech-industry/next-generation-chip-passes-key-milestone/">"Next-generation chip passes key milestone"</a>. <a href="CNET" title="CNET">CNET News</a>.</cite>

</li>

<li id="cite_note-69"><a href="#cite_ref-69">^</a> <cite id="CITEREFKanellos1999" class="citation web cs1">Kanellos, Michael (October 4, 1999). <a rel="nofollow" class="external text" href="https://www.cnet.com/tech/tech-industry/intel-names-merced-chip-itanium/">"Intel names Merced chip Itanium"</a>. <a href="CNET" title="CNET">CNET</a>. Retrieved April 30, 2007.</cite>

</li>

<li id="cite_note-70"><a href="#cite_ref-70">^</a> <cite id="CITEREFFinstad1999" class="citation newsgroup cs1">Finstad, Kraig (October 4, 1999). <a rel="nofollow" class="external text" href="https://groups.google.com/d/msg/comp.sys.mac.advocacy/UiOOaXF3-lI/f3nje9CHPx0J">"Re:Itanium"</a>. <a href="Usenet_newsgroup" title="Usenet newsgroup">Newsgroup</a>: <a rel="nofollow" class="external text" href="news:comp.sys.mac.advocacy">comp.sys.mac.advocacy</a>. Retrieved May 20, 2020.</cite>

</li>

<li id="cite_note-Reg_Itanic-71"><a href="#cite_ref-Reg_Itanic_71-0">^</a> <cite id="CITEREFSherriff1999" class="citation news cs1">Sherriff, Pete (October 28, 1999). <a rel="nofollow" class="external text" href="https://www.theregister.com/1999/10/28/amd_vs_intel_our_readers/">"AMD vs Intel – our readers write"</a>. <a href="The_Register" title="The Register">The Register</a>. Retrieved November 25, 2022.</cite>

</li>

<li id="cite_note-72"><a href="#cite_ref-72">^</a> <cite id="CITEREFBerlind2001" class="citation web cs1">Berlind, David (November 30, 2001). <a rel="nofollow" class="external text" href="https://www.zdnet.com/article/interpreting-mcnealys-lexicon/">"Interpreting McNealy's lexicon"</a>. <a href="ZDNet" class="mw-redirect" title="ZDNet">ZDNet</a> Tech Update. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190904215102/https://www.zdnet.com/article/interpreting-mcnealys-lexicon/">Archived</a> from the original on September 4, 2019. Retrieved March 19, 2007.</cite>

</li>

<li id="cite_note-73"><a href="#cite_ref-73">^</a> <cite id="CITEREFDemerjian2006" class="citation web cs1 cs1-prop-unfit">Demerjian, Charlie (July 18, 2006). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160305085136/http://www.theinquirer.net/inquirer/news/1004260/itanic-shell-game-continues">"Itanic shell game continues"</a>. <a href="The_Inquirer" title="The Inquirer">The Inquirer</a>. Archived from the original on March 5, 2016. Retrieved February 27, 2016.</cite>

</li>

<li id="cite_note-74"><a href="#cite_ref-74">^</a> <cite id="CITEREFMorgenson2003" class="citation news cs1">Morgenson, Gretchen (October 19, 2003). <a rel="nofollow" class="external text" href="https://www.nytimes.com/2003/10/19/business/market-watch-fawning-analysts-betray-investors.html">"Fawning Analysts Betray Investors"</a>. <a href="The_New_York_Times" title="The New York Times">The New York Times</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20121011211448/http://www.zdnet.com/news/interpreting-mcnealys-lexicon/296322">Archived</a> from the original on October 11, 2012. Retrieved January 1, 2019.</cite>

</li>

<li id="cite_note-75"><a href="#cite_ref-75">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20040719063719/http://developer.intel.com/design/pcn/Processors/D0102840.pdf">"Product Change Notification"</a> (PDF). Intel. Archived from <a rel="nofollow" class="external text" href="http://developer.intel.com/design/pcn/Processors/D0102840.pdf">the original</a> (PDF) on 2004-07-19.</cite>

</li>

<li id="cite_note-76"><a href="#cite_ref-76">^</a> <cite id="CITEREFNiccolai2001" class="citation web cs1">Niccolai, James (IDG News Service) (29 May 2001). <a rel="nofollow" class="external text" href="https://www.computerworld.com/article/2582076/intel-officially-launches-64-bit-itanium-chip.html">"Intel officially launches 64-bit Itanium chip"</a>. <a href="Computerworld" title="Computerworld">Computerworld</a>. Retrieved 30 March 2022.</cite>

</li>

<li id="cite_note-77"><a href="#cite_ref-77">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.zdnet.com/article/server-makers-tout-itanium-models-5000117490/">"Server makers tout Itanium models"</a>. <a href="ZDNet" class="mw-redirect" title="ZDNet">ZDNet</a>. Retrieved 30 March 2022.</cite>

</li>

<li id="cite_note-78"><a href="#cite_ref-78">^</a> <cite id="CITEREFLinley_Gwennap2001" class="citation magazine cs1">Linley Gwennap (June 4, 2001). <a rel="nofollow" class="external text" href="https://www.eetimes.com/itanium-era-dawns/">"Itanium era dawns"</a>. EE Times. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20191217201629/https://www.eetimes.com/itanium-era-dawns/">Archived</a> from the original on December 17, 2019. Retrieved December 17, 2019.</cite>

</li>

<li id="cite_note-Thunder-79">^ <a href="#cite_ref-Thunder_79-0">a</a> <a href="#cite_ref-Thunder_79-1">b</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20060925041933/http://www.top500.org/system/ranking/5597">"Titan Cluster Itanium 800 MHz"</a>. <a href="TOP500" title="TOP500">TOP500</a> web site. Archived from <a rel="nofollow" class="external text" href="http://www.top500.org/system/ranking/5597">the original</a> on September 25, 2006. Retrieved May 16, 2007.</cite>

</li>

<li id="cite_note-80"><a href="#cite_ref-80">^</a> <cite id="CITEREFMichael_Kanellos2001" class="citation news cs1">Michael Kanellos (December 11, 2001). <a rel="nofollow" class="external text" href="https://www.cnet.com/tech/tech-industry/itanium-sales-off-to-a-slow-start/">"Itanium sales off to a slow start"</a>. CNET News. Retrieved July 4, 2023.</cite>

</li>

<li id="cite_note-81"><a href="#cite_ref-81">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20040719080318/http://developer.intel.com/design/pcn/Processors/D0103649.pdf">"Product Change Notification"</a> (PDF). Intel. Archived from <a rel="nofollow" class="external text" href="http://developer.intel.com/design/pcn/Processors/D0103649.pdf">the original</a> (PDF) on 2004-07-19.</cite>

</li>

<li id="cite_note-82"><a href="#cite_ref-82">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20060313054448/http://developer.intel.com/design/pcn/Processors/D0105835.pdf">"Product Change Notification"</a> (PDF). Intel. Archived from <a rel="nofollow" class="external text" href="http://developer.intel.com/design/pcn/Processors/D0105835.pdf">the original</a> (PDF) on 2006-03-13.</cite>

</li>

<li id="cite_note-83"><a href="#cite_ref-83">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://qdms.intel.com/dm/i.aspx/53B15559-69D6-4DD5-8379-0ABE33DCE8D4/PCN107564-00.pdf">"Product Change Notification"</a> (PDF). Intel. Warning: forced download. Retrieved 28 April 2022.</cite>

</li>

<li id="cite_note-84"><a href="#cite_ref-84">^</a> McKinley: 16 April 2004<a href="#cite_note-81">[77]</a> Madison 6M: 28 July 2006<a href="#cite_note-82">[78]</a> Madison 9M: 16 November 2007<a href="#cite_note-83">[79]</a>

</li>

<li id="cite_note-85"><a href="#cite_ref-85">^</a> <cite id="CITEREFHammondNaffziger" class="citation web cs1">Hammond, Gary; Naffziger, Sam. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20030706123550/http://intel.com/design/itanium2/download/McK-IDF-2001.pdf">"Next Generation Itanium™ Processor Overview"</a> (PDF). Archived from <a rel="nofollow" class="external text" href="http://intel.com/design/itanium2/download/McK-IDF-2001.pdf">the original</a> (PDF) on 6 July 2003.</cite>

</li>

<li id="cite_note-86"><a href="#cite_ref-86">^</a> <cite id="CITEREFNaffzingerColon-BonetFischerRiedlinger2002" class="citation journal cs1">Naffzinger, Samuel D.; Colon-Bonet, Glenn T.; Fischer, Timothy; Riedlinger, Reid; Sullivan, Thomas J.; Grutkowski, Tom (November 2002). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20030322045555/http://cpus.hp.com/technical_references/jssc_naffziger.pdf">"The implementation of the Itanium 2 microprocessor"</a> (PDF). <a href="IEEE_Journal_of_Solid-State_Circuits" title="IEEE Journal of Solid-State Circuits">IEEE Journal of Solid-State Circuits</a>. 37 (11): 1448–1460. <a href="Bibcode_(identifier)" class="mw-redirect" title="Bibcode (identifier)">Bibcode</a>:<a rel="nofollow" class="external text" href="https://ui.adsabs.harvard.edu/abs/2002IJSSC..37.1448N">2002IJSSC..37.1448N</a>. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FJSSC.2002.803943">10.1109/JSSC.2002.803943</a>. Archived from <a rel="nofollow" class="external text" href="http://cpus.hp.com/technical_references/jssc_naffziger.pdf">the original</a> (PDF) on 2003-03-22.</cite>

</li>

<li id="cite_note-87"><a href="#cite_ref-87">^</a> <cite id="CITEREFSoltisGibson" class="citation web cs1">Soltis, Don; Gibson, Mark. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20050531030015/http://www.hotchips.org/archives/hc14/2_Mon/03_soltis.pdf">"Itanium® 2 Processor Microarchitecture Overview"</a> (PDF). <a href="Hot_Chips" class="mw-redirect" title="Hot Chips">Hot Chips</a>. Archived from <a rel="nofollow" class="external text" href="http://www.hotchips.org/archives/hc14/2_Mon/03_soltis.pdf">the original</a> (PDF) on 31 May 2005.</cite>

</li>

<li id="cite_note-88"><a href="#cite_ref-88">^</a> <cite id="CITEREFNaffzigerHammond" class="citation web cs1">Naffziger, Samuel; Hammond, Gary. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20041029174655/http://www.imec.be/elela/HD03/examens/2003/D20_6.pdf">"The Implementation of the Next-Generation 64b Itanium Microprocessor"</a> (PDF). Archived from <a rel="nofollow" class="external text" href="http://www.imec.be/elela/HD03/examens/2003/D20_6.pdf">the original</a> (PDF) on 29 October 2004.</cite>

</li>

<li id="cite_note-89"><a href="#cite_ref-89">^</a> <cite id="CITEREFKrazit2003" class="citation web cs1">Krazit, Tom (12 May 2003). <a rel="nofollow" class="external text" href="https://www.computerworld.com/article/2570015/intel-details-itanium-2-bug.html">"Intel details Itanium 2 bug"</a>. <a href="Computerworld" title="Computerworld">Computerworld</a>. Retrieved 30 March 2022.</cite>

</li>

<li id="cite_note-ISA-90"><a href="#cite_ref-ISA_90-0">^</a> <cite class="citation web cs1 cs1-prop-unfit"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20080908015727/http://www.itaniumsolutionsalliance.org/">"Itanium Solutions Alliance"</a>. ISA web site. Archived from the original on September 8, 2008. Retrieved May 16, 2007.</cite>

</li>

<li id="cite_note-91"><a href="#cite_ref-91">^</a> <cite id="CITEREFScott2006" class="citation web cs1">Scott, Bilepo (January 26, 2006). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120111011444/http://www.ednasia.com/article-12139-computingleadersannouncestrategyforneweraofmissioncriticalcomputing-Asia.html">"Computing Leaders Announce Strategy for New Era of Mission Critical Computing"</a>. Itanium Solutions Alliance Press Release. Archived from <a rel="nofollow" class="external text" href="http://www.ednasia.com/article-12139-computingleadersannouncestrategyforneweraofmissioncriticalcomputing-Asia.html">the original</a> on January 11, 2012. Retrieved October 16, 2008.</cite>

</li>

<li id="cite_note-92"><a href="#cite_ref-92">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.cpu-world.com/news_2011/2011021601_Intel_server_processors_to_be_discontinued_in_2012.html">"Intel server processors to be discontinued in 2012"</a>. CPU-World. Retrieved 28 April 2022.</cite>

</li>

<li id="cite_note-93"><a href="#cite_ref-93">^</a> <cite id="CITEREFKanellos" class="citation web cs1">Kanellos, Michael. <a rel="nofollow" class="external text" href="https://www.cnet.com/tech/tech-industry/intel-accelerates-itanium-schedule/">"Intel accelerates Itanium schedule"</a>. <a href="CNET" title="CNET">CNET</a>. Retrieved 3 April 2022.</cite>

</li>

<li id="cite_note-qa-94">^ <a href="#cite_ref-qa_94-0">a</a> <a href="#cite_ref-qa_94-1">b</a> <cite id="CITEREFShanklandKanellos2003" class="citation news cs1">Shankland, Stephen; Kanellos, Michael (9 July 2003). <a rel="nofollow" class="external text" href="https://www.theglobeandmail.com/technology/intels-summer-of-servers/article1163609/">"Intel's summer of servers"</a>. <a href="The_Globe_and_Mail" title="The Globe and Mail">The Globe and Mail</a>. Retrieved 27 April 2022.</cite>

</li>

<li id="cite_note-monty-95">^ <a href="#cite_ref-monty_95-0">a</a> <a href="#cite_ref-monty_95-1">b</a> <cite id="CITEREFKanellos" class="citation web cs1">Kanellos, Michael. <a rel="nofollow" class="external text" href="https://www.cnet.com/tech/tech-industry/intel-fills-in-more-details-on-itanium-family/">"Intel fills in more details on Itanium family"</a>. <a href="CNET" title="CNET">CNET</a>. Retrieved 3 April 2022.</cite>

</li>

<li id="cite_note-96"><a href="#cite_ref-96">^</a> <cite id="CITEREFWilson" class="citation web cs1">Wilson, Derek. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20210917112245/https://www.anandtech.com/show/1465/3">"Intel Developer Forum Fall 2004: Day 1 Keynote"</a>. <a href="AnandTech" title="AnandTech">AnandTech</a>. Archived from <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/1465/3">the original</a> on September 17, 2021. Retrieved 28 April 2022.</cite>

</li>

<li id="cite_note-97"><a href="#cite_ref-97">^</a> <cite id="CITEREFShankland" class="citation news cs1">Shankland, Stephen. <a rel="nofollow" class="external text" href="https://www.cnet.com/tech/tech-industry/intel-pushes-back-itanium-chips-revamps-xeon/">"Intel pushes back Itanium chips, revamps Xeon"</a>. <a href="CNET" title="CNET">CNET</a>. Retrieved 3 April 2022.</cite>

</li>

<li id="cite_note-CW1-98">^ <a href="#cite_ref-CW1_98-0">a</a> <a href="#cite_ref-CW1_98-1">b</a> <cite id="CITEREFNiccolai2008" class="citation web cs1">Niccolai, James (May 20, 2008). <a rel="nofollow" class="external text" href="https://www.computerworld.com/article/2536018/-tukwila--itanium-servers-due-early-next-year--intel-says.html">"'Tukwila' Itanium servers due early next year, Intel says"</a>. <a href="Computerworld" title="Computerworld">Computerworld</a>. Retrieved September 26, 2022.</cite>

</li>

<li id="cite_note-IW1-99"><a href="#cite_ref-IW1_99-0">^</a> <cite id="CITEREFGonsalves2007" class="citation web cs1">Gonsalves, Antone (November 1, 2007). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120310003352/http://www.informationweek.com/">"Intel Unveils Seven Itanium Processors"</a>. <a href="InformationWeek" title="InformationWeek">InformationWeek</a>. Archived from <a rel="nofollow" class="external text" href="http://www.informationweek.com/story/showArticle.jhtml?articleID=202800983">the original</a> on March 10, 2012. Retrieved November 6, 2007.</cite>

</li>

<li id="cite_note-idf04f-100">^ <a href="#cite_ref-idf04f_100-0">a</a> <a href="#cite_ref-idf04f_100-1">b</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/pressroom/archive/releases/2004/20040907corp_a.htm">"Intel Shares Findings, Platform Plans To Better Guide Businesses Through 'Transformation'"</a>. Intel.</cite>

</li>

<li id="cite_note-101"><a href="#cite_ref-101">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/pressroom/archive/releases/2004/20041216comp.htm">"Intel Strengthens Investment In Intel® Itanium® Architecture With Hiring Of HP Design Team"</a>.</cite>

</li>

<li id="cite_note-102"><a href="#cite_ref-102">^</a> <cite id="CITEREFShilov" class="citation web cs1">Shilov, Anton. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190201050122/https://www.anandtech.com/show/13924/intel-to-discontinue-itanium-9700-kittson-processor-the-last-itaniums">"Intel to Discontinue Itanium 9700 'Kittson' Processor, the Last of the Itaniums"</a>. <a href="AnandTech" title="AnandTech">AnandTech</a>. Archived from <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/13924/intel-to-discontinue-itanium-9700-kittson-processor-the-last-itaniums">the original</a> on February 1, 2019. Retrieved 28 April 2022.</cite>

</li>

<li id="cite_note-103"><a href="#cite_ref-103">^</a> <cite id="CITEREFKanellos" class="citation web cs1">Kanellos, Michael. <a rel="nofollow" class="external text" href="https://www.cnet.com/tech/tech-industry/intel-changes-code-name-of-future-itanium/">"Intel changes code name of future Itanium"</a>. <a href="CNET" title="CNET">CNET</a>. Retrieved 4 July 2023.</cite>

</li>

<li id="cite_note-104"><a href="#cite_ref-104">^</a> <cite id="CITEREFMcMillan2003" class="citation web cs1">McMillan, Robert (18 December 2003). <a rel="nofollow" class="external text" href="https://www.infoworld.com/article/2678103/trademark-flap-prompts-intel-to-rename-tanglewood.html">"Trademark flap prompts Intel to rename Tanglewood"</a>. <a href="InfoWorld" title="InfoWorld">InfoWorld</a>. Retrieved 31 March 2022.</cite>

</li>

<li id="cite_note-105"><a href="#cite_ref-105">^</a> <cite id="CITEREFVance" class="citation news cs1"><a href="Ashlee_Vance" title="Ashlee Vance">Vance, Ashlee</a>. <a rel="nofollow" class="external text" href="https://www.theregister.com/2003/05/01/tanglewood_to_run_10x_faster1/">"Tanglewood to run 10x faster than Madison"</a>. <a href="The_Register" title="The Register">The Register</a>. Retrieved 27 April 2022.</cite>

</li>

<li id="cite_note-106"><a href="#cite_ref-106">^</a> <cite id="CITEREFMcMillan2003" class="citation web cs1">McMillan, Robert (17 September 2003). <a rel="nofollow" class="external text" href="https://www.infoworld.com/article/2676169/fall-idf--intel-readies-8-core--16-core-itanium-2.html">"FALL IDF: Intel readies 8-core, 16-core Itanium 2"</a>. <a href="InfoWorld" title="InfoWorld">InfoWorld</a>. Retrieved 31 March 2022.</cite>

</li>

<li id="cite_note-107"><a href="#cite_ref-107">^</a> <cite id="CITEREFShankland" class="citation web cs1">Shankland, Stephen. <a rel="nofollow" class="external text" href="https://www.cnet.com/tech/tech-industry/tanglewood-to-top-intel-chip-show/">"'Tanglewood' to top Intel chip show"</a>. <a href="CNET" title="CNET">CNET</a>. Retrieved 31 March 2022.</cite>

</li>

<li id="cite_note-108"><a href="#cite_ref-108">^</a> <cite id="CITEREFMcMillan" class="citation web cs1">McMillan, Robert. <a rel="nofollow" class="external text" href="https://www.computerweekly.com/news/2240053525/Itanium-2-Montecito-to-be-multithreaded">"Itanium 2 Montecito to be multithreaded"</a>. <a href="Computer_Weekly" title="Computer Weekly">Computer Weekly</a>. Retrieved 31 March 2022.</cite>

</li>

<li id="cite_note-109"><a href="#cite_ref-109">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/pressroom/archive/releases/2004/20040218corp.htm">"Intel Outlines Platform Innovations For More Manageable, Balanced And Secure Enterprise Computing"</a>. Intel.</cite>

</li>

<li id="cite_note-110"><a href="#cite_ref-110">^</a> <cite id="CITEREFShankland" class="citation web cs1">Shankland, Stephen. <a rel="nofollow" class="external text" href="https://www.cnet.com/tech/tech-industry/intel-to-spotlight-new-itanium-poulson/">"Intel to spotlight new Itanium: 'Poulson'"</a>. <a href="CNET" title="CNET">CNET</a>. Retrieved 31 March 2022.</cite>

</li>

<li id="cite_note-CSI-111"><a href="#cite_ref-CSI_111-0">^</a> <cite id="CITEREFMerritt2005" class="citation magazine cs1">Merritt, Rick (March 2, 2005). <a rel="nofollow" class="external text" href="https://www.eetimes.com/intel-preps-hypertransport-competitor-for-xeon-itanium-cpus/">"Intel preps HyperTransport competitor for Xeon, Itanium CPUs"</a>. EE Times. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20191217201715/https://www.eetimes.com/intel-preps-hypertransport-competitor-for-xeon-itanium-cpus/">Archived</a> from the original on December 17, 2019. Retrieved December 17, 2019.</cite>

</li>

<li id="cite_note-112"><a href="#cite_ref-112">^</a> <cite id="CITEREFVance" class="citation news cs1"><a href="Ashlee_Vance" title="Ashlee Vance">Vance, Ashlee</a>. <a rel="nofollow" class="external text" href="https://www.theregister.com/2005/10/28/intel_whitefield_india/">"Intel's Xeon chip kill is result of chaos in India"</a>. <a href="The_Register" title="The Register">The Register</a>. Retrieved 28 April 2022.</cite>

</li>

<li id="cite_note-zdnet_2005_slip-113"><a href="#cite_ref-zdnet_2005_slip_113-0">^</a> <cite id="CITEREFShankland2005" class="citation web cs1">Shankland, Stephen (October 24, 2005). <a rel="nofollow" class="external text" href="https://www.zdnet.com/article/intel-pushes-back-itanium-chips-revamps-xeon/">"Intel pushes back Itanium chips, revamps Xeon"</a>. <a href="ZDNet" class="mw-redirect" title="ZDNet">ZDNet</a> News. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200802000438/https://www.zdnet.com/article/intel-pushes-back-itanium-chips-revamps-xeon/">Archived</a> from the original on August 2, 2020. Retrieved January 1, 2019.</cite>

</li>

<li id="cite_note-INQ09-114"><a href="#cite_ref-INQ09_114-0">^</a> <cite id="CITEREFDemerjian2009" class="citation web cs1 cs1-prop-unfit">Demerjian, Charlie (May 21, 2009). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20090523101543/http://www.theinquirer.net/inquirer/news/1137434/tukwila-delayed-2010">"Tukwila delayed until 2010"</a>. <a href="The_Inquirer" title="The Inquirer">The Inquirer</a>. Archived from the original on May 23, 2009. Retrieved May 21, 2009.</cite>

</li>

<li id="cite_note-eweek-tukwila-115"><a href="#cite_ref-eweek-tukwila_115-0">^</a> <cite id="CITEREFBurt2010" class="citation web cs1">Burt, Jeff (February 8, 2010). <a rel="nofollow" class="external text" href="https://www.eweek.com/networking/new-intel-itanium-offers-greater-performance-memory-capacity/">"New Intel Itanium Offers Greater Performance, Memory Capacity"</a>. <a href="EWeek" title="EWeek">eWeek</a>.</cite>

</li>

<li id="cite_note-Kittson-116">^ <a href="#cite_ref-Kittson_116-0">a</a> <a href="#cite_ref-Kittson_116-1">b</a> <cite id="CITEREFTan2007" class="citation web cs1">Tan, Aaron (June 15, 2007). <a rel="nofollow" class="external text" href="https://www.zdnet.com/article/intel-updates-itanium-line-with-kittson/">"Intel updates Itanium line with 'Kittson'"</a>. <a href="ZDNet" class="mw-redirect" title="ZDNet">ZDNet</a>. Retrieved June 15, 2007.</cite>

</li>

<li id="cite_note-TukwilaDelay-117"><a href="#cite_ref-TukwilaDelay_117-0">^</a> <cite id="CITEREFStokes2009" class="citation web cs1">Stokes, Jon (February 5, 2009). <a rel="nofollow" class="external text" href="https://arstechnica.com/business/news/2009/02/intel-delays-quad-itanium-to-boost-platform-memory-capacity.ars">"Intel delays quad Itanium to boost platform memory capacity"</a>. ars technica. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120122093011/http://arstechnica.com/business/news/2009/02/intel-delays-quad-itanium-to-boost-platform-memory-capacity.ars">Archived</a> from the original on January 22, 2012. Retrieved February 5, 2009.</cite>

</li>

<li id="cite_note-DailyTech_Server-118"><a href="#cite_ref-DailyTech_Server_118-0">^</a> <cite id="CITEREFNg2009" class="citation news cs1">Ng, Jansen (February 10, 2009). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20090213150005/http://www.dailytech.com/intel+aims+for+efficiency+with+new+server+roadmap/article14224.htm">"Intel Aims for Efficiency With New Server Roadmap"</a>. <a href="DailyTech" title="DailyTech">DailyTech</a>. Archived from <a rel="nofollow" class="external text" href="http://www.dailytech.com/Intel+Aims+for+Efficiency+With+New+Server+Roadmap/article14224.htm">the original</a> on February 13, 2009. Retrieved February 10, 2009.</cite>

</li>

<li id="cite_note-119"><a href="#cite_ref-119">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20160304054256/http://www.xbitlabs.com/news/cpu/display/20120201201109_HP_Paid_Intel_690_Million_to_Keep_Itanium_Alive_Court_Findings.html">"HP Paid Intel $690 Million to Keep Itanium Alive - Court Findings"</a>. Archived from <a rel="nofollow" class="external text" href="http://www.xbitlabs.com/news/cpu/display/20120201201109_HP_Paid_Intel_690_Million_to_Keep_Itanium_Alive_Court_Findings.html">the original</a> on March 4, 2016.</cite>

</li>

<li id="cite_note-120"><a href="#cite_ref-120">^</a> <cite id="CITEREFRobert_McMillan2012" class="citation magazine cs1">Robert McMillan (February 1, 2012). <a rel="nofollow" class="external text" href="https://www.wired.com/wiredenterprise/2012/02/hp-itanium/">"HP Paid Intel $690 Million To Keep Itanium On Life Support"</a>. <a href="Wired_(magazine)" title="Wired (magazine)">Wired</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20140306014953/http://www.wired.com/wiredenterprise/2012/02/hp-itanium/">Archived</a> from the original on March 6, 2014. Retrieved March 7, 2017.</cite>

</li>

<li id="cite_note-121"><a href="#cite_ref-121">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/pressroom/archive/releases/2005/20050301corp_a.htm">"Intel Platforms, Technologies To Drive Enterprise Advances"</a>. Intel. Retrieved 31 March 2022.</cite>

</li>

<li id="cite_note-mercury-122">^ <a href="#cite_ref-mercury_122-0">a</a> <a href="#cite_ref-mercury_122-1">b</a> <cite id="CITEREFBoslet2007" class="citation web cs1">Boslet, Mark (15 June 2007). <a rel="nofollow" class="external text" href="https://www.mercurynews.com/2007/06/14/intel-to-employ-advanced-technology-on-server-chips/">"Intel to employ advanced technology on server chips"</a>. <a href="The_Mercury_News" title="The Mercury News">The Mercury News</a>. Retrieved 26 February 2022.</cite>

</li>

<li id="cite_note-dx.doi.org-123">^ <a href="#cite_ref-dx.doi.org_123-0">a</a> <a href="#cite_ref-dx.doi.org_123-1">b</a> <cite id="CITEREFRiedlingerBhatiaBiroBowhill2011" class="citation conference cs1">Riedlinger, Reid J.; Bhatia, Rohit; Biro, Larry; Bowhill, Bill; Fetzer, Eric; Gronowski, Paul; Grutkowski, Tom (February 24, 2011). "A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers". 2011 IEEE International Solid-State Circuits Conference. 2011 IEEE International Solid-State Circuits Conference. pp. 84–86. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FISSCC.2011.5746230">10.1109/ISSCC.2011.5746230</a>. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-1-61284-303-2</bdi>.</cite>

</li>

<li id="cite_note-124"><a href="#cite_ref-124">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20171201034615/http://isscc.org/wp-content/uploads/sites/10/2017/05/ISSCC2011_AdvanceProgram.pdf">"ISSCC 2011"</a> (PDF). Archived from <a rel="nofollow" class="external text" href="http://isscc.org/wp-content/uploads/sites/10/2017/05/ISSCC2011_AdvanceProgram.pdf">the original</a> (PDF) on December 1, 2017. Retrieved November 17, 2017.</cite>

</li>

<li id="cite_note-125"><a href="#cite_ref-125">^</a> <cite id="CITEREFKanter2010" class="citation web cs1">Kanter, David (November 17, 2010). <a rel="nofollow" class="external text" href="https://www.realworldtech.com/poulson-preview/">"New Itanium Microarchitecture at ISSCC 2011"</a>. Real World Tech. Retrieved July 4, 2023.</cite>

</li>

<li id="cite_note-126"><a href="#cite_ref-126">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://itpeernetwork.intel.com/itanium-poulson-update-greater-parallelism-new-instruction-replay-more-catch-the-details-from-hotchips/">"Itanium Poulson Update — Greater Parallelism, New Instruction Replay & More: Catch the details from Hotchips!"</a>. August 19, 2011. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180627144340/https://itpeernetwork.intel.com/itanium-poulson-update-greater-parallelism-new-instruction-replay-more-catch-the-details-from-hotchips/">Archived</a> from the original on June 27, 2018. Retrieved November 17, 2017.</cite>

</li>

<li id="cite_note-127"><a href="#cite_ref-127">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.slideshare.net/PaulineNist/intel-itanium-poulson-update-at-hotchips">"Intel Itanium Hotchips 2011 Overview"</a>. 18 August 2011. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120214131459/http://www.slideshare.net/PaulineNist/intel-itanium-poulson-update-at-hotchips">Archived</a> from the original on 14 February 2012. Retrieved January 23, 2012.</cite>

</li>

<li id="cite_note-poulson-the-future-of-itanium-servers-128">^ <a href="#cite_ref-poulson-the-future-of-itanium-servers_128-0">a</a> <a href="#cite_ref-poulson-the-future-of-itanium-servers_128-1">b</a> <cite id="CITEREFKanter2011" class="citation web cs1">Kanter, David (May 18, 2011). <a rel="nofollow" class="external text" href="https://www.realworldtech.com/poulson/">"Poulson: The Future of Itanium Servers"</a>. Real World Tech. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20121102093620/http://www.realworldtech.com/poulson/">Archived</a> from the original on November 2, 2012. Retrieved November 9, 2012.</cite>

</li>

<li id="cite_note-HotChip-Poulson-129"><a href="#cite_ref-HotChip-Poulson_129-0">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20120324101540/http://newsroom.intel.com/servlet/JiveServlet/download/38-5835/Hot%20Chips%20%20Poulson%20disclosure%20Factsheet.pdf">"Hot Chips Poulson Disclosure Factsheet"</a> (PDF). Intel press release. August 19, 2011. Archived from <a rel="nofollow" class="external text" href="http://newsroom.intel.com/servlet/JiveServlet/download/38-5835/Hot%20Chips%20%20Poulson%20disclosure%20Factsheet.pdf">the original</a> (PDF) on March 24, 2012. Retrieved August 19, 2011.</cite>

</li>

<li id="cite_note-130"><a href="#cite_ref-130">^</a> <cite id="CITEREFMerrit2010" class="citation magazine cs1">Merrit, Rick (November 23, 2010). <a rel="nofollow" class="external text" href="https://www.eetimes.com/researchers-carve-cpu-into-plastic-foil/">"Researchers carve CPU into plastic foil"</a>. EE Times. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20191217201623/https://www.eetimes.com/researchers-carve-cpu-into-plastic-foil/">Archived</a> from the original on December 17, 2019. Retrieved December 17, 2019.</cite>

</li>

<li id="cite_note-131"><a href="#cite_ref-131">^</a> <cite id="CITEREFO'Brien2011" class="citation web cs1">O'Brien, Terrence (August 22, 2011). <a rel="nofollow" class="external text" href="https://www.engadget.com/2011/08/22/intel-talks-up-next-gen-itanium-32nm-8-core-poulson/">"Intel talks up next-gen Itanium: 32nm, 8-core Poulson"</a>. <a href="Engadget" title="Engadget">Engadget</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180421163456/https://www.engadget.com/2011/08/22/intel-talks-up-next-gen-itanium-32nm-8-core-poulson/">Archived</a> from the original on April 21, 2018. Retrieved April 30, 2012.</cite>

</li>

<li id="cite_note-cpu-world.com-132">^ <a href="#cite_ref-cpu-world.com_132-0">a</a> <a href="#cite_ref-cpu-world.com_132-1">b</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.cpu-world.com/news_2012/2012061301_Unreleased_Intel_Itanium_9500-series_CPUs_spotted.html">"Unreleased Intel Itanium 9500-series CPUs spotted"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20171122032035/http://www.cpu-world.com/news_2012/2012061301_Unreleased_Intel_Itanium_9500-series_CPUs_spotted.html">Archived</a> from the original on 2017-11-22. Retrieved 2012-08-02.</cite>

</li>

<li id="cite_note-133"><a href="#cite_ref-133">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.cpu-world.com/news_2012/2012062601_Spotted_9500-series_CPUs_confirmed_to_be_Poulson_Itaniums.html">"Spotted 9500-series CPUs confirmed to be "Poulson" Itaniums"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20171006152039/http://www.cpu-world.com/news_2012/2012062601_Spotted_9500-series_CPUs_confirmed_to_be_Poulson_Itaniums.html">Archived</a> from the original on 2017-10-06. Retrieved 2012-08-02.</cite>

</li>

<li id="cite_note-134"><a href="#cite_ref-134">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.cpu-world.com/news_2012/2012071101_Intel_publishes_Itanium_9500_reference_manual.html">"Intel publishes Itanium 9500 reference manual"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20171008075849/http://www.cpu-world.com/news_2012/2012071101_Intel_publishes_Itanium_9500_reference_manual.html">Archived</a> from the original on 2017-10-08. Retrieved 2012-08-02.</cite>

</li>

<li id="cite_note-135"><a href="#cite_ref-135">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://ark.intel.com/products/codename/26643/Poulson">"Products formerly Poulson"</a>. Intel® ARK (Product Specs). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170518065154/http://ark.intel.com/products/codename/26643/Poulson">Archived</a> from the original on May 18, 2017. Retrieved May 31, 2017.</cite>

</li>

<li id="cite_note-136"><a href="#cite_ref-136">^</a> <cite id="CITEREFWheeler" class="citation web cs1">Wheeler, Bob. <a rel="nofollow" class="external text" href="https://www.linleygroup.com/newsletters/newsletter_detail.php?num=4912">"Tocking Itanium"</a>. <a href="Microprocessor_Report" title="Microprocessor Report">The Linley Group</a>. Retrieved 26 February 2022.</cite>

</li>

<li id="cite_note-137"><a href="#cite_ref-137">^</a> <cite id="CITEREFSkaugen" class="citation web cs1">Skaugen, Kirk. <a rel="nofollow" class="external text" href="https://download.intel.com/newsroom/kits/idf/2011_fall/pdfs/Kirk_Skaugen_DCSG_MegaBriefing.pdf">"IDF2011 Intel Developer Forum"</a> (PDF). slide 21. Intel. Retrieved 26 February 2022.</cite>

</li>

<li id="cite_note-138"><a href="#cite_ref-138">^</a> <cite id="CITEREFNist" class="citation web cs1">Nist, Pauline. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200808053527/https://itpeernetwork.intel.com/more-than-just-another-itanium-chip/#gs.r3sxvd">"More than just another Itanium chip"</a>. Intel. Archived from <a rel="nofollow" class="external text" href="https://itpeernetwork.intel.com/more-than-just-another-itanium-chip/#gs.r3sxvd">the original</a> on 8 August 2020. Retrieved 26 February 2022.</cite>

</li>

<li id="cite_note-139"><a href="#cite_ref-139">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20161109135111/http://www.intel.com/content/www/us/en/processors/itanium/itanium-kittson-update.html">"Intel® Itanium® Processors Update"</a>. Archived from <a rel="nofollow" class="external text" href="http://www.intel.com/content/www/us/en/processors/itanium/itanium-kittson-update.html">the original</a> on 9 November 2016.</cite>

</li>

<li id="cite_note-kitguru-140">^ <a href="#cite_ref-kitguru_140-0">a</a> <a href="#cite_ref-kitguru_140-1">b</a> <cite id="CITEREFShilov2015" class="citation web cs1">Shilov, Anton (April 17, 2015). <a rel="nofollow" class="external text" href="https://www.kitguru.net/components/cpu/anton-shilov/intel-still-committed-to-make-new-itanium-processors/">"Intel still committed to make new Itanium processors"</a>. kitguru.net. Retrieved July 4, 2023. <q>KitGuru Says: Even though it is highly likely that "Kittson" chips will be released, it does not seem that Intel and HP actually want to invest R&D money in boosting performance of IA-64 chips. As a result, it looks like the best thing "Kittson" will offer will be a 20 per cent performance improvement over current gen offerings.</q></cite>

</li>

<li id="cite_note-141"><a href="#cite_ref-141">^</a> <cite id="CITEREFShah2014" class="citation web cs1">Shah, Agam (February 19, 2014). <a rel="nofollow" class="external text" href="http://www.pcworld.com/article/2099260/intels-new-xeon-server-chip-pushes-itanium-closer-to-end.html">"Intel's new Xeon server chip pushes Itanium closer to death's door"</a>. pcworld.com. PC World. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160126165249/http://www.pcworld.com/article/2099260/intels-new-xeon-server-chip-pushes-itanium-closer-to-end.html">Archived</a> from the original on January 26, 2016. Retrieved January 13, 2016.</cite>

</li>

<li id="cite_note-142"><a href="#cite_ref-142">^</a> <cite id="CITEREFShilov" class="citation web cs1">Shilov, Anton. <a rel="nofollow" class="external text" href="https://www.kitguru.net/professional/server/anton-shilov/hp-mission-critical-servers-business-improves-as-itanium-fades-away/">"HP: mission-critical servers business improves as Itanium fades away"</a>. Kitguru. Retrieved 30 March 2022.</cite>

</li>

<li id="cite_note-143"><a href="#cite_ref-143">^</a> <cite id="CITEREFShah2014" class="citation web cs1">Shah, Agam (2 December 2014). <a rel="nofollow" class="external text" href="https://www.computerworld.com/article/2853998/hp-sees-hp-ux-sticking-around-for-10-years.html">"HP sees HP-UX sticking around for 10 years"</a>. <a href="Computerworld" title="Computerworld">Computerworld</a>. Retrieved 30 March 2022.</cite>

</li>

<li id="cite_note-144"><a href="#cite_ref-144">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www-ssl.intel.com/content/www/us/en/products/processors/itanium.html">"Intel® Itanium® Processor"</a>. Intel. Retrieved May 15, 2017.</cite>

</li>

<li id="cite_note-145"><a href="#cite_ref-145">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/9300-9500-9700-series-spec-update.pdf">"Intel® Itanium® Processor 9300, 9500 and 9700 Series Specification Update"</a> (PDF). Intel. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20201111234308/https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/9300-9500-9700-series-spec-update.pdf">Archived</a> (PDF) from the original on 11 November 2020.</cite>

</li>

<li id="cite_note-146"><a href="#cite_ref-146">^</a> <cite id="CITEREFCutress2017" class="citation news cs1">Cutress, Ian (May 11, 2017). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170511152533/http://www.anandtech.com/show/11372/intels-itanium-takes-one-last-breath-9700-series-released">"Intel's Itanium Takes One Last Breath: Itanium 9700 Series CPUs Released"</a>. Anandtech. Archived from <a rel="nofollow" class="external text" href="http://www.anandtech.com/show/11372/intels-itanium-takes-one-last-breath-9700-series-released">the original</a> on May 11, 2017. Retrieved May 11, 2017.</cite>

</li>

<li id="cite_note-147"><a href="#cite_ref-147">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/codename/32203/kittson.html">"Products formerly Kittson"</a>. Intel® ARK (Product Specs). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190804134312/https://ark.intel.com/content/www/us/en/ark/products/codename/32203/kittson.html">Archived</a> from the original on August 4, 2019. Retrieved May 15, 2017.</cite>

</li>

<li id="cite_note-148"><a href="#cite_ref-148">^</a> <cite id="CITEREFPatrizio2007" class="citation web cs1">Patrizio, Andy (October 12, 2007). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180422062117/http://www.internetnews.com/ent-news/article.php/3705016">"Intel Plows Forward With Itanium"</a>. InternetNews.com. Archived from <a rel="nofollow" class="external text" href="http://www.internetnews.com/ent-news/article.php/3705016">the original</a> on April 22, 2018. Retrieved October 18, 2007.</cite>

</li>

<li id="cite_note-149"><a href="#cite_ref-149">^</a> <a href="International_Data_Corporation" class="mw-redirect" title="International Data Corporation">IDC</a> World Wide Server Tracker, Q2'08

</li>

<li id="cite_note-vance_late-150">^ <a href="#cite_ref-vance_late_150-0">a</a> <a href="#cite_ref-vance_late_150-1">b</a> <a href="#cite_ref-vance_late_150-2">c</a> <a href="#cite_ref-vance_late_150-3">d</a> <cite id="CITEREFVance2009" class="citation news cs1"><a href="Ashlee_Vance" title="Ashlee Vance">Vance, Ashlee</a> (February 9, 2009). <a rel="nofollow" class="external text" href="https://bits.blogs.nytimes.com/2009/02/09/ten-years-after-first-delay-intels-itanium-is-still-late/">"Ten Years After First Delay, Intel's Itanium Is Still Late"</a>. <a href="The_New_York_Times" title="The New York Times">The New York Times</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110710101259/http://bits.blogs.nytimes.com/2009/02/09/ten-years-after-first-delay-intels-itanium-is-still-late/">Archived</a> from the original on July 10, 2011. Retrieved April 1, 2010.</cite>

</li>

<li id="cite_note-151"><a href="#cite_ref-151">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.pcworld.com/article/2028587/intel-shifts-gears-on-itanium-raising-questions-about-the-server-chips-future.html">"Intel shifts gears on Itanium, raising questions about the server chip's future"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20130615180648/http://www.pcworld.com/article/2028587/intel-shifts-gears-on-itanium-raising-questions-about-the-server-chips-future.html">Archived</a> from the original on 2013-06-15. Retrieved 2013-08-04.</cite>

</li>

<li id="cite_note-152"><a href="#cite_ref-152">^</a> <cite id="CITEREFVance2006" class="citation web cs1"><a href="Ashlee_Vance" title="Ashlee Vance">Vance, Ashlee</a> (June 1, 2006). <a rel="nofollow" class="external text" href="https://www.theregister.com/2006/06/01/itanic_q1_gartner/">"HP grabs 90% of 'industry standard' Itanic market"</a>. <a href="The_Register" title="The Register">The Register</a>. Retrieved November 25, 2022.</cite>

</li>

<li id="cite_note-153"><a href="#cite_ref-153">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://support.intel.com/support/motherboards/server/SR9000MK4U/sb/CS-023638.htm">"Intel Server System SR9000MK4U Technical Product Specification"</a>. <a href="Intel" title="Intel">Intel</a> web site. January 2007. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20090208174924/http://support.intel.com/support/motherboards/server/SR9000MK4U/sb/CS-023638.htm">Archived</a> from the original on February 8, 2009. Retrieved April 14, 2007.</cite>

</li>

<li id="cite_note-eol-154"><a href="#cite_ref-eol_154-0">^</a> <cite id="CITEREFAleksandar2021" class="citation web cs1">Aleksandar, Kostovic (2021-07-31). <a rel="nofollow" class="external text" href="https://www.tomshardware.com/news/last-itanium-shipment">"Itanium Waves Goodbye As Intel Delivers Last Shipments of Now Forgotten Processor Family"</a>. Tom's Hardware. Retrieved 2022-11-29.</cite>

</li>

<li id="cite_note-155"><a href="#cite_ref-155">^</a> <cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://secure64.com/not-vulnerable-intel-itanium-secure64-sourcet/">"Not Vulnerable - Intel Itanium/Secure64 SourceT - Secure 64"</a>. Secure 64. January 9, 2018. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20181004103818/https://secure64.com/not-vulnerable-intel-itanium-secure64-sourcet/">Archived</a> from the original on October 4, 2018. Retrieved October 4, 2018.</cite>

</li>

<li id="cite_note-157"><a href="#cite_ref-157">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20060621013059/http://download.intel.com/design/Itanium2/datashts/25094505.pdf">"Intel® Itanium® 2 Processor Datasheet"</a> (PDF). Intel. p. 9. Archived from <a rel="nofollow" class="external text" href="http://download.intel.com/design/Itanium2/datashts/25094505.pdf">the original</a> (PDF) on 21 June 2006.</cite>

</li>

<li id="cite_note-158"><a href="#cite_ref-158">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110607124058/http://download.intel.com/design/Itanium2/datashts/31405401.pdf">"Dual-Core Intel® Itanium® 2 Processor 9000 Series Datasheet"</a> (PDF). Intel. p. 9. Archived from <a rel="nofollow" class="external text" href="http://download.intel.com/design/Itanium2/datashts/31405401.pdf">the original</a> (PDF) on 7 June 2011.</cite>

</li>

<li id="cite_note-159"><a href="#cite_ref-159">^</a> <cite id="CITEREFMorgan" class="citation news cs1">Morgan, Timothy Prickett. <a rel="nofollow" class="external text" href="https://www.theregister.com/2013/02/08/intel_kills_itanium_xeon_convergence_and_kittson/">"Remember that Xeon E7-Itanium convergence? FUHGEDDABOUDIT"</a>. <a href="The_Register" title="The Register">The Register</a>. Retrieved November 25, 2022.</cite>

</li>

<li id="cite_note-ibm_ditching_itanium-160">^ <a href="#cite_ref-ibm_ditching_itanium_160-0">a</a> <a href="#cite_ref-ibm_ditching_itanium_160-1">b</a> <cite id="CITEREFShankland2005" class="citation news cs1">Shankland, Stephen (February 25, 2005). <a rel="nofollow" class="external text" href="https://www.cnet.com/tech/tech-industry/sources-ibm-ditching-itanium-altogether/">"Sources: IBM ditching Itanium altogether"</a>. <a href="CNET" title="CNET">CNET News</a>. Retrieved July 4, 2023.</cite>

</li>

<li id="cite_note-161"><a href="#cite_ref-161">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20040723073549/http://developer.intel.com/design/itanium/downloads/24870301.pdf">"Intel 460GX Chipset Datasheet"</a> (PDF). Intel. Archived from <a rel="nofollow" class="external text" href="http://developer.intel.com/design/itanium/downloads/24870301.pdf">the original</a> (PDF) on 23 July 2004.</cite>

</li>

<li id="cite_note-162"><a href="#cite_ref-162">^</a> <cite id="CITEREFMuellerSoperSosinsky2006" class="citation book cs1">Mueller, Scott; Soper, Mark Edward; Sosinsky, Barrie (2006). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=9cLFf_1PBnkC&pg=PT301">Upgrading and Repairing Servers</a>. Pearson Education. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>0-13-279698-8</bdi>. Retrieved 6 April 2022.</cite>

</li>

<li id="cite_note-163"><a href="#cite_ref-163">^</a> <cite id="CITEREFShimpi" class="citation web cs1">Shimpi, Anand Lal. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110729150352/http://www.anandtech.com/show/465">"Intel's 820 Chipset - Performance using SDRAM"</a>. <a href="AnandTech" title="AnandTech">AnandTech</a>. Archived from <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/465">the original</a> on July 29, 2011. Retrieved 6 April 2022.</cite>

</li>

<li id="cite_note-164"><a href="#cite_ref-164">^</a> <cite id="CITEREFShimpi" class="citation web cs1">Shimpi, Anand Lal. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110419010747/http://www.anandtech.com/show/551">"Rambus DRAM Part 2: Performance"</a>. <a href="AnandTech" title="AnandTech">AnandTech</a>. Archived from <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/551">the original</a> on April 19, 2011. Retrieved 6 April 2022.</cite>

</li>

<li id="cite_note-165"><a href="#cite_ref-165">^</a> <cite id="CITEREFBriggs2002" class="citation journal cs1">Briggs, Fayé; et al. (7 August 2002). "Intel 870: a building block for cost-effective, scalable servers". <a href="IEEE_Micro" title="IEEE Micro">IEEE Micro</a>. 22 (2 (March–April)): 36–47. <a href="CiteSeerX_(identifier)" class="mw-redirect" title="CiteSeerX (identifier)">CiteSeerX</a> <a rel="nofollow" class="external text" href="https://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.140.2915">10.1.1.140.2915</a>. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FMM.2002.997878">10.1109/MM.2002.997878</a>. <a href="S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:3201355">3201355</a>.</cite>

</li>

<li id="cite_note-166"><a href="#cite_ref-166">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20040701014149/http://www.intel.com/design/chipsets/datashts/25111203.pdf">"Intel® E8870 Scalable Node Controller (SNC) Datasheet"</a> (PDF). Intel. Archived from <a rel="nofollow" class="external text" href="http://www.intel.com/design/chipsets/datashts/25111203.pdf">the original</a> (PDF) on 1 July 2004.</cite>

</li>

<li id="cite_note-167"><a href="#cite_ref-167">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20030706004227/http://intel.com/design/chipsets/datashts/25111103.pdf">"Intel® E8870IO Server I/O Hub (SIOH) Datasheet"</a> (PDF). Intel. Archived from <a rel="nofollow" class="external text" href="http://intel.com/design/chipsets/datashts/25111103.pdf">the original</a> (PDF) on 6 July 2003.</cite>

</li>

<li id="cite_note-168"><a href="#cite_ref-168">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/pressroom/archive/releases/2004/20040218corp.htm">"Intel Outlines Platform Innovations For More Manageable, Balanced And Secure Enterprise Computing"</a>. Intel. Retrieved 7 April 2022.</cite>

</li>

<li id="cite_note-169"><a href="#cite_ref-169">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20030319214329/http://www.hp.com/products1/itanium/infolibrary/whitepapers/5981_2240EN.pdf">"Overview of the new Itanium® 2-based HP servers rx2600 and rx5670: how HP is putting Intel® Itanium 2 processors to work"</a> (PDF). Hewlett-Packard. p. 17. Archived from <a rel="nofollow" class="external text" href="http://www.hp.com/products1/itanium/infolibrary/whitepapers/5981_2240EN.pdf">the original</a> (PDF) on 19 March 2003.</cite>

</li>

<li id="cite_note-170"><a href="#cite_ref-170">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20061029145359/http://h18000.www1.hp.com/products/quickspecs/12141_div/12141_div.PDF">"HP Integrity rx2620 Server"</a> (PDF). Archived from <a rel="nofollow" class="external text" href="http://h18000.www1.hp.com/products/quickspecs/12141_div/12141_div.PDF">the original</a> (PDF) on 29 October 2006.</cite>

</li>

<li id="cite_note-171"><a href="#cite_ref-171">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20060314004913/http://h18000.www1.hp.com/products/quickspecs/11847_div/11847_div.PDF">"HP Integrity rx4640-8 Server"</a> (PDF). Archived from <a rel="nofollow" class="external text" href="http://h18000.www1.hp.com/products/quickspecs/11847_div/11847_div.PDF">the original</a> (PDF) on 14 March 2006.</cite>

</li>

<li id="cite_note-172"><a href="#cite_ref-172">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20041209002029/http://www.hp.com/products1/servers/integrity/entry_level/rx5670/index.html">"HP Integrity rx5670 Server summary"</a>. Archived from <a rel="nofollow" class="external text" href="http://www.hp.com/products1/servers/integrity/entry_level/rx5670/index.html">the original</a> on 9 December 2004.</cite>

</li>

<li id="cite_note-173"><a href="#cite_ref-173">^</a> <cite id="CITEREFTurnerRau" class="citation web cs1">Turner, Vernon; Rau, Shane. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20050601104604/http://h71028.www7.hp.com/ERC/downloads/sx1000_White_Paper_.pdf">"HP's sx1000 Chipset: Innovation Atop Standardization"</a> (PDF). <a href="International_Data_Group" title="International Data Group">IDC</a> (sponsored by HP). Archived from <a rel="nofollow" class="external text" href="http://h71028.www7.hp.com/ERC/downloads/sx1000_White_Paper_.pdf">the original</a> (PDF) on 1 June 2005.</cite>

</li>

<li id="cite_note-174"><a href="#cite_ref-174">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20040731205815/http://www.hp.com/products1/servers/integrity/superdome_high_end/infolibrary/Superdome_wp.pdf">"Meet the HP Integrity Superdome: A white paper from HP"</a> (PDF). Archived from <a rel="nofollow" class="external text" href="http://www.hp.com/products1/servers/integrity/superdome_high_end/infolibrary/Superdome_wp.pdf">the original</a> (PDF) on 31 July 2004.</cite>

</li>

<li id="cite_note-175"><a href="#cite_ref-175">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20050509234702/http://h21007.www2.hp.com/dspp/files/unprotected/integritymidrangejan05.pdf">"Itanium®–based midrange servers from HP— the HP Integrity rx7620-16 and rx8620-32 Servers"</a> (PDF). Archived from <a rel="nofollow" class="external text" href="http://h21007.www2.hp.com/dspp/files/unprotected/integritymidrangejan05.pdf">the original</a> (PDF) on 9 May 2005.</cite>

</li>

<li id="cite_note-176"><a href="#cite_ref-176">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://archive.org/details/manualzilla-id-7031299">"User Service Guide HP Integrity Superdome/sx2000 and HP 9000 Superdome/sx2000 Servers"</a>. <a href="Hewlett-Packard" title="Hewlett-Packard">Hewlett-Packard</a>. September 2009 – via Internet Archive.</cite>

</li>

<li id="cite_note-177"><a href="#cite_ref-177">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://shoredata.us.com/wp-content/uploads/2016/03/rx6600.pdf">"Overview of the HP Integrity rx2660, rx3600, and rx6600 Servers"</a> (PDF). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170306041015/https://shoredata.us.com/wp-content/uploads/2016/03/rx6600.pdf">Archived</a> (PDF) from the original on 2017-03-06.</cite>

</li>

<li id="cite_note-178"><a href="#cite_ref-178">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20220708214847/https://www.hp.com/ch-de/pdf/harness_family_brosch_re_4aa3-4519enw_tcm_179_1247486.pdf">"HP Integrity systems Family guide"</a> (PDF). Archived from <a rel="nofollow" class="external text" href="https://www.hp.com/ch-de/pdf/harness_family_brosch_re_4aa3-4519enw_tcm_179_1247486.pdf">the original</a> (PDF) on 8 July 2022. Retrieved 24 May 2022.</cite>

</li>

<li id="cite_note-179"><a href="#cite_ref-179">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://lenovopress.com/sg247056.pdf">"IBM Eserver xSeries 455 Planning and Installation Guide"</a> (PDF). IBM/Lenovo. Retrieved 6 April 2022.</cite>

</li>

<li id="cite_note-180"><a href="#cite_ref-180">^</a> <cite id="CITEREFWoodacreRobbRoeFeind" class="citation web cs1">Woodacre, Michael; Robb, Derek; Roe, Dean; Feind, Karl. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20060314142114/http://www.sgi.com/pdfs/3474.pdf">"The SGI® Altix 3000 Global Shared-Memory Architecture"</a> (PDF). sgi.com. Archived from <a rel="nofollow" class="external text" href="http://www.sgi.com/pdfs/3474.pdf">the original</a> (PDF) on 2006-03-14.</cite>

</li>

<li id="cite_note-181"><a href="#cite_ref-181">^</a> <cite id="CITEREFVogelsang" class="citation web cs1">Vogelsang, Reiner. <a rel="nofollow" class="external text" href="https://moodle.risc.jku.at/file.php/50/altix_hardware.pdf">"SGI® Altix™ Hardware Architecture"</a> (PDF). Retrieved 25 April 2022.</cite>

</li>

<li id="cite_note-182"><a href="#cite_ref-182">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20160121032040/http://techpubs.sgi.com/library/manuals/4000/007-4660-002/pdf/007-4660-002.pdf">"SGI® Altix™ 350 System User's Guide"</a> (PDF). Archived from <a rel="nofollow" class="external text" href="http://techpubs.sgi.com/library/manuals/4000/007-4660-002/pdf/007-4660-002.pdf">the original</a> (PDF) on 2016-01-21.</cite>

</li>

<li id="cite_note-183"><a href="#cite_ref-183">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20060314165928/http://www.sgi.com/pdfs/3392.pdf">"SGI® Altix® 3000 Servers and Superclusters"</a> (PDF). Archived from <a rel="nofollow" class="external text" href="http://www.sgi.com/pdfs/3392.pdf">the original</a> (PDF) on 2006-03-14.</cite>

</li>

<li id="cite_note-184"><a href="#cite_ref-184">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20051124042540/http://www.sgi.com/pdfs/3867.pdf">"SGI® Altix® 4700 Servers and Supercomputers"</a> (PDF). Archived from <a rel="nofollow" class="external text" href="http://www.sgi.com/pdfs/3867.pdf">the original</a> (PDF) on 2005-11-24.</cite>

</li>

<li id="cite_note-185"><a href="#cite_ref-185">^</a> <cite id="CITEREFVogelsang" class="citation web cs1">Vogelsang, Reiner. <a rel="nofollow" class="external text" href="https://wwwuser.gwdg.de/~parallel/parallelrechner/altix_documentation/Altix_Hardware_revised_4.pdf">"SGI® Altix™ Hardware Architecture"</a> (PDF). Retrieved 4 July 2023.</cite>

</li>

<li id="cite_note-186"><a href="#cite_ref-186">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20151203105150/http://techpubs.sgi.com/library/manuals/3000/007-3938-006/pdf/007-3938-006.pdf">"SGI® L1 and L2 Controller Software User's Guide"</a> (PDF). Archived from <a rel="nofollow" class="external text" href="http://techpubs.sgi.com/library/manuals/3000/007-3938-006/pdf/007-3938-006.pdf">the original</a> (PDF) on 2015-12-03.</cite>

</li>

<li id="cite_note-187"><a href="#cite_ref-187">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.netbsd.org/ports/">"Platforms Supported by NetBSD"</a>. www.netbsd.org. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20210227091416/http://www.netbsd.org/ports/">Archived</a> from the original on 2021-02-27. Retrieved 2021-03-02.</cite>

</li>

<li id="cite_note-188"><a href="#cite_ref-188">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://wiki.netbsd.org/ports/ia64/">"NetBSD/ia64"</a>. wiki.netbsd.org. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180427122809/http://wiki.netbsd.org/ports/ia64/">Archived</a> from the original on 2018-04-27. Retrieved 2021-03-02.</cite>

</li>

<li id="cite_note-Sabbagh-189">^ <a href="#cite_ref-Sabbagh_189-0">a</a> <a href="#cite_ref-Sabbagh_189-1">b</a> <cite id="CITEREFSabbagh2000" class="citation web cs1">Sabbagh, Dan (3 Feb 2000). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20070930200218/http://www.vnunet.com/vnunet/news/2111194/trillian-releases-linux-code-itanium">"Trillian releases Linux code for Itanium"</a>. vnunet.com. Archived from <a rel="nofollow" class="external text" href="http://www.vnunet.com/vnunet/news/2111194/trillian-releases-linux-code-itanium">the original</a> on 30 September 2007. Retrieved 2007-03-20.</cite>

</li>

<li id="cite_note-190"><a href="#cite_ref-190">^</a> <cite class="citation pressrelease cs1"><a rel="nofollow" class="external text" href="https://www.redhat.com/en/about/press-releases/press-trillian">"Leading Linux Distributors Join the Trillian Project"</a>. Red Hat (Press release). December 20, 1999. Retrieved 2007-03-20.</cite>

</li>

<li id="cite_note-191"><a href="#cite_ref-191">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.irisa.fr/caps/projects/ArchiCompil/iato/">"IATO simulation environment"</a>.</cite>

</li>

<li id="cite_note-192"><a href="#cite_ref-192">^</a> <cite id="CITEREFShankland2005" class="citation web cs1">Shankland, Stephen (22 March 2005). <a rel="nofollow" class="external text" href="https://www.cnet.com/culture/fedora-for-itanium-taking-baby-steps/">"Fedora for Itanium taking baby steps"</a>. CNET. Retrieved 2023-07-04.</cite>

</li>

<li id="cite_note-193"><a href="#cite_ref-193">^</a> <cite id="CITEREFConnor2005" class="citation web cs1">Connor, Deni (2005-01-06). <a rel="nofollow" class="external text" href="https://www.networkworld.com/article/2328219/novell-releases-suse-linux-for-hp-itanium-servers.html">"Novell releases SuSE Linux for HP Itanium servers"</a>. Network World. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20211029172431/https://www.networkworld.com/article/2328219/novell-releases-suse-linux-for-hp-itanium-servers.html">Archived</a> from the original on 2021-10-29. Retrieved 2021-10-14.</cite>

</li>

<li id="cite_note-194"><a href="#cite_ref-194">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.itpro.co.uk/110119/centos-5-linux-released">"CentOS 5 Linux released"</a>. IT PRO. 14 April 2007. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20211029170900/https://www.itpro.co.uk/110119/centos-5-linux-released">Archived</a> from the original on 2021-10-29. Retrieved 2021-10-14.</cite>

</li>

<li id="cite_note-195"><a href="#cite_ref-195">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.ports.debian.org">"Debian Ports"</a>. Retrieved 2024-10-27.</cite>

</li>

<li id="cite_note-196"><a href="#cite_ref-196">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://epic-slack.org/#!index.md#2024-05-15">"Slackware for IA-64 is here! Get E P I C !"</a>. 2024-05-15. Retrieved 2025-01-26.</cite>

</li>

<li id="cite_note-197"><a href="#cite_ref-197">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://wiki.gentoo.org/wiki/Project:IA-64">"Project:IA-64"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180916235508/https://wiki.gentoo.org/wiki/Project:IA-64">Archived</a> from the original on 2018-09-16. Retrieved 2015-07-12. <q>The Gentoo/IA-64 Project works to keep Gentoo the most up to date and fastest IA-64 distribution available.</q></cite>

</li>

<li id="cite_note-198"><a href="#cite_ref-198">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://projects.gentoo.org/council/meeting-logs/20240721-summary.txt">"Summary of Gentoo Council meeting 2024-07-21"</a>. Retrieved 2024-08-15. <q>The Council members agreed on deprecated ia64 arch</q></cite>

</li>

<li id="cite_note-199"><a href="#cite_ref-199">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://t2sde.org/#news-2024-12-19">"T2 24.12 "Sky's the Limit!""</a>. 2024-12-19. Retrieved 2025-01-26. <q>Support and stability was improved for SPARC64, Intel Itanium IA-64, Sony PS3, [...]</q></cite>

</li>

<li id="cite_note-red-hat-to-drop-itanium-200"><a href="#cite_ref-red-hat-to-drop-itanium_200-0">^</a> <cite id="CITEREFRicknäs2009" class="citation web cs1">Ricknäs, Mikael (2009-12-21). <a rel="nofollow" class="external text" href="https://www.computerworld.com/article/2522241/red-hat-to-drop-itanium-support-in-enterprise-linux-6.html">"Red Hat to drop Itanium support in Enterprise Linux 6"</a>. <a href="Computerworld" title="Computerworld">Computerworld</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20211028172143/https://www.computerworld.com/article/2522241/red-hat-to-drop-itanium-support-in-enterprise-linux-6.html">Archived</a> from the original on 2021-10-28. Retrieved 2021-10-14.</cite>

</li>

<li id="cite_note-201"><a href="#cite_ref-201">^</a> <cite id="CITEREFClark" class="citation web cs1">Clark, Jack. <a rel="nofollow" class="external text" href="https://www.zdnet.com/article/sparc-and-itanium-support-discontinued-in-ubuntu-10-10/">"SPARC and Itanium support discontinued in Ubuntu 10.10"</a>. ZDNet. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20211029180056/https://www.zdnet.com/article/sparc-and-itanium-support-discontinued-in-ubuntu-10-10/">Archived</a> from the original on 2021-10-29. Retrieved 2021-10-14.</cite>

</li>

<li id="cite_note-202"><a href="#cite_ref-202">^</a> <cite id="CITEREFAnderson" class="citation news cs1">Anderson, Tim. <a rel="nofollow" class="external text" href="https://www.theregister.com/2021/02/01/linux_pulls_itanium_support/">"'It's dead, Jim': Torvalds marks Intel Itanium processors as orphaned in Linux kernel"</a>. <a href="The_Register" title="The Register">The Register</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20211029174912/https://www.theregister.com/2021/02/01/linux_pulls_itanium_support/">Archived</a> from the original on 2021-10-29. Retrieved 2021-10-14.</cite>

</li>

<li id="cite_note-203"><a href="#cite_ref-203">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=228345bf98cd78f91d007478a51f9a471489e44a">"kernel/git/torvalds/linux.git - Linux kernel source tree"</a>. <a href="Kernel.org" title="Kernel.org">kernel.org</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20211103183816/https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=228345bf98cd78f91d007478a51f9a471489e44a">Archived</a> from the original on 2021-11-03. Retrieved 2021-10-14.</cite>

</li>

<li id="cite_note-204"><a href="#cite_ref-204">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=cf8e8658100d4eae80ce9b21f7a81cb024dd5057">"kernel/git/next/linux-next.git - The linux-next integration testing tree"</a>. git.kernel.org. Retrieved 2023-09-18.</cite>

</li>

<li id="cite_note-205"><a href="#cite_ref-205">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.phoronix.com/news/Linux-6.7-To-Drop-Itanium-IA-64">"Linux 6.7 Set To Drop Support For Itanium IA-64"</a>. www.phoronix.com. Retrieved 2023-09-18.</cite>

</li>

<li id="cite_note-206"><a href="#cite_ref-206">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://github.com/linux-ia64/">"linux-ia64"</a>. GitHub. Retrieved October 1, 2024. <q>Maintenance and development of the Linux operating system for Intel Itanium architecture (IA-64)</q></cite>

</li>

<li id="cite_note-207"><a href="#cite_ref-207">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://epic-linux.org/">"EPIC Linux"</a>. Retrieved October 1, 2024.</cite>

</li>

<li id="cite_note-208"><a href="#cite_ref-208">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20060302213751/http://h71000.www7.hp.com/openvmstimes/openvmstimes.pdf">"Compaq OpenVMS Times"</a> (PDF). January 2002. Archived from <a rel="nofollow" class="external text" href="http://h71000.www7.hp.com/openvmstimes/openvmstimes.pdf">the original</a> (PDF) on March 2, 2006.</cite>

</li>

<li id="cite_note-ia64-port-209">^ <a href="#cite_ref-ia64-port_209-0">a</a> <a href="#cite_ref-ia64-port_209-1">b</a> <a href="#cite_ref-ia64-port_209-2">c</a> <cite id="CITEREFClair_Grant2005" class="citation journal cs1">Clair Grant (June 2005). <a rel="nofollow" class="external text" href="http://www.decus.de/events/alphamigration/vortraege/porting_openvms_to_integrity.pdf">"Porting OpenVMS to HP Integrity Servers"</a> (PDF). OpenVMS Technical Journal. 6. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20211122133713/http://www.decus.de/events/alphamigration/vortraege/porting_openvms_to_integrity.pdf">Archived</a> (PDF) from the original on 2021-11-22. Retrieved 2021-11-22.</cite>

</li>

<li id="cite_note-VSI.CW2014-210"><a href="#cite_ref-VSI.CW2014_210-0">^</a> <cite id="CITEREFPatrick_Thibodeau2014" class="citation news cs1">Patrick Thibodeau (July 31, 2014). <a rel="nofollow" class="external text" href="https://www.computerworld.com/article/2490683/operating-systems-hp-gives-openvms-new-life.html">"HP gives OpenVMS new life"</a>. <a href="Computerworld" title="Computerworld">Computerworld</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20211030234001/https://www.computerworld.com/article/2490683/operating-systems-hp-gives-openvms-new-life.html">Archived</a> from the original on 2021-10-30. Retrieved 2021-10-21.</cite>

</li>

<li id="cite_note-211"><a href="#cite_ref-211">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://support.hpe.com/hpesc/public/docDisplay?docId=a00083646en_us">"OpenVMS Roadmap"</a>. HPE. July 2019. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20211122133712/https://support.hpe.com/hpesc/public/docDisplay?docId=a00083646en_us">Archived</a> from the original on 2021-11-22. Retrieved 2021-11-22.</cite>

</li>

<li id="cite_note-vsi-roadmap-212">^ <a href="#cite_ref-vsi-roadmap_212-0">a</a> <a href="#cite_ref-vsi-roadmap_212-1">b</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://vmssoftware.com/about/roadmap/">"OpenVMS – A guide to the strategy and roadmap"</a>. VSI. Retrieved 2025-05-13.</cite>

</li>

<li id="cite_note-213"><a href="#cite_ref-213">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.hpe.com/psnow/doc/4AA0-6149ENW">"HPE NonStop OS"</a>. HPE. April 2018. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20211122135935/https://www.hpe.com/psnow/doc/4AA0-6149ENW">Archived</a> from the original on 2021-11-22. Retrieved 2021-11-22.</cite>

</li>

<li id="cite_note-hpe-brochure-214"><a href="#cite_ref-hpe-brochure_214-0">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://assets.ext.hpe.com/is/content/hpedam/documents/4aa4-2000-2999/4aa4-2988/4aa4-2988enw.pdf">"HPE NonStop family of systems"</a> (PDF). HPE. May 2021. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220121201745/https://assets.ext.hpe.com/is/content/hpedam/documents/4aa4-2000-2999/4aa4-2988/4aa4-2988enw.pdf">Archived</a> (PDF) from the original on 2022-01-21. Retrieved 2021-11-22.</cite>

</li>

<li id="cite_note-215"><a href="#cite_ref-215">^</a> <cite id="CITEREFPrashanth_Kamath_U2019" class="citation web cs1">Prashanth Kamath U (2019-07-30). <a rel="nofollow" class="external text" href="https://connect2nonstop.com/2371-2/">"News from HPE's NonStop Enterprise Division"</a>. The Connection. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20211122140545/https://connect2nonstop.com/2371-2/">Archived</a> from the original on 2021-11-22. Retrieved 2021-11-22.</cite>

</li>

<li id="cite_note-216"><a href="#cite_ref-216">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.phoronix.com/scan.php?page=news_item&px=Intel-IA-64-GCC-Deprecation">"Intel Itanium IA-64 Support To Be Deprecated By GCC 10, Planned Removal In GCC 11"</a>. Phoronix. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200711001829/https://www.phoronix.com/scan.php?page=news_item&px=Intel-IA-64-GCC-Deprecation">Archived</a> from the original on 2020-07-11. Retrieved 2020-07-09.</cite>

</li>

<li id="cite_note-217"><a href="#cite_ref-217">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://github.com/llvm/llvm-project/commit/17151155ed8f83dcbb5db69bca2839ac2da19e0e">"Remove the IA-64 backend. · llvm/llvm-project@1715115 · GitHub"</a>. GitHub. Jul 24, 2009.</cite>

</li>

<li id="cite_note-218"><a href="#cite_ref-218">^</a> <cite id="CITEREFNovakovic2008" class="citation web cs1 cs1-prop-unfit">Novakovic, Nebojsa (September 25, 2008). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20080927080239/http://www.theinquirer.net/gb/inquirer/news/2008/09/24/idc-performance-computing">"Supercomputing now dominated by X86 architecture"</a>. <a href="The_Inquirer" title="The Inquirer">The Inquirer</a>. Archived from the original on September 27, 2008. Retrieved September 27, 2008.</cite>

</li>

<li id="cite_note-219"><a href="#cite_ref-219">^</a> <cite id="CITEREFButler2008" class="citation web cs1">Butler, Andrew (October 3, 2008). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20090214114712/http://www.gartner.com/DisplayDocument?ref=g_rss&id=770312">"Preparing for Tukwila: The Next Generation of Intel's Itanium Processor Family"</a>. Archived from <a rel="nofollow" class="external text" href="http://www.gartner.com/DisplayDocument?ref=g_rss&id=770312">the original</a> on February 14, 2009. Retrieved October 21, 2008.</cite>

</li>

<li id="cite_note-220"><a href="#cite_ref-220">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.top500.org/statistics/list/">"Processor Generation / Itanium 2 Montecito"</a>. <a href="TOP500" title="TOP500">TOP500</a> web site. Retrieved June 6, 2022.</cite> Select "June 2012" and "Processor Generation"

</li>

<li id="cite_note-221"><a href="#cite_ref-221">^</a> <cite id="CITEREFVance2004" class="citation news cs1"><a href="Ashlee_Vance" title="Ashlee Vance">Vance, Ashlee</a> (May 6, 2004). <a rel="nofollow" class="external text" href="https://www.theregister.com/2004/05/06/hp_mx2_itaniummodule/">"HP rides Hondo to super-sized Itanium servers"</a>. <a href="The_Register" title="The Register">The Register</a>. Retrieved November 25, 2022.</cite>

</li>

<li id="cite_note-222"><a href="#cite_ref-222">^</a> <cite class="citation pressrelease cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20121112014247/http://newsroom.intel.com/community/intel_newsroom/blog/2012/11/08/new-intel-itanium-processor-9500-delivers-breakthrough-capabilities-for-mission-critical-computing">"New Intel Itanium Processor 9500 Delivers Breakthrough Capabilities for Mission-Critical Computing"</a> (Press release). Intel. Archived from <a rel="nofollow" class="external text" href="http://newsroom.intel.com/community/intel_newsroom/blog/2012/11/08/new-intel-itanium-processor-9500-delivers-breakthrough-capabilities-for-mission-critical-computing">the original</a> on November 12, 2012. Retrieved November 9, 2012.</cite>

</li>

<li id="cite_note-223"><a href="#cite_ref-223">^</a> <cite id="CITEREFShilov" class="citation web cs1">Shilov, Anton. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20121110213532/http://www.xbitlabs.com/news/cpu/display/20121108120233_Intel_Launches_Eight_Core_Itanium_9500_Poulson_Mission_Critical_Server_Processor.html">"Intel Launches Eight-Core Itanium 9500 "Poulson" Mission-Critical Server Processor"</a>. X-bit Labs. Archived from <a rel="nofollow" class="external text" href="http://www.xbitlabs.com/news/cpu/display/20121108120233_Intel_Launches_Eight_Core_Itanium_9500_Poulson_Mission_Critical_Server_Processor.html">the original</a> on November 10, 2012. Retrieved November 9, 2012.</cite>

</li>

<li id="cite_note-224"><a href="#cite_ref-224">^</a> <cite id="CITEREFUndy" class="citation web cs1">Undy, Steve. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20130616020413/http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/itanium-9500-massive-parallelism-mission-critical-computing-paper.pdf">"WHITE PAPER Intel Itanium Processor 9500 Series"</a> (PDF). Intel. Archived from <a rel="nofollow" class="external text" href="http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/itanium-9500-massive-parallelism-mission-critical-computing-paper.pdf">the original</a> (PDF) on June 16, 2013. Retrieved November 9, 2012.</cite>

</li>

<li id="cite_note-225"><a href="#cite_ref-225">^</a> <cite id="CITEREFOrlowski2001" class="citation news cs1">Orlowski, Andrew (January 23, 2001). <a rel="nofollow" class="external text" href="https://www.theregister.com/2001/01/23/benchmarks_itanic_32bit_emulation/">"Benchmarks – Itanic 32bit emulation is 'unusable'. No kidding — slower than a P100"</a>. <a href="The_Register" title="The Register">The Register</a>. Retrieved November 25, 2022.</cite>

</li>

<li id="cite_note-226"><a href="#cite_ref-226">^</a> <cite id="CITEREFDvorak2009" class="citation web cs1"><a href="John_C._Dvorak" title="John C. Dvorak">Dvorak, John C.</a> (January 26, 2009). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120608105627/http://www.pcmag.com/article.aspx/curl/2339629">"How the Itanium Killed the Computer Industry"</a>. <a href="PC_Mag" class="mw-redirect" title="PC Mag">PC Mag</a>. Archived from <a rel="nofollow" class="external text" href="https://www.pcmag.com/article.aspx/curl/2339629">the original</a> on June 8, 2012. Retrieved April 15, 2012.</cite>

</li>

<li id="cite_note-227"><a href="#cite_ref-227">^</a> <cite id="CITEREFKnuth2008" class="citation web cs1">Knuth, Donald E. (April 25, 2008). <a rel="nofollow" class="external text" href="http://www.informit.com/articles/article.aspx?p=1193856">"Interview with Donald Knuth"</a>. InformIT. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20210223015337/https://www.informit.com/articles/article.aspx?p=1193856">Archived</a> from the original on February 23, 2021. Retrieved April 1, 2010.</cite>

</li>

<li id="cite_note-last_ms-228"><a href="#cite_ref-last_ms_228-0">^</a> <cite id="CITEREFReger2010" class="citation web cs1">Reger, Dan (April 2, 2010). <a rel="nofollow" class="external text" href="https://cloudblogs.microsoft.com/windowsserver/2010/04/02/windows-server-2008-r2-to-phase-out-itanium/">"Windows Server 2008 R2 to Phase Out Itanium"</a>. Windows Server Blog. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180613111922/https://cloudblogs.microsoft.com/windowsserver/2010/04/02/windows-server-2008-r2-to-phase-out-itanium/">Archived</a> from the original on June 13, 2018. Retrieved July 29, 2018.</cite>

</li>

<li id="cite_note-last_rhel-229"><a href="#cite_ref-last_rhel_229-0">^</a> <cite id="CITEREFMorgan2009" class="citation news cs1">Morgan, Timothy Prickett (December 18, 2009). <a rel="nofollow" class="external text" href="https://www.theregister.com/2009/12/18/redhat_rhel6_itanium_dead/">"Red Hat pulls plug on Itanium with RHEL 6"</a>. <a href="The_Register" title="The Register">The Register</a>. Retrieved November 25, 2022.</cite>

</li>

<li id="cite_note-pcworld2011-230"><a href="#cite_ref-pcworld2011_230-0">^</a> <cite id="CITEREFNystedt2011" class="citation web cs1">Nystedt, Dan (March 22, 2011). <a rel="nofollow" class="external text" href="https://www.pcworld.com/article/495910/article-2090.html">"Oracle stops developing software for Intel's Itanium Chips"</a>. <a href="PC_World" title="PC World">PC World</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20211230101153/https://www.pcworld.com/article/495910/article-2090.html">Archived</a> from the original on December 30, 2021. Retrieved December 30, 2021.</cite>

</li>

<li id="cite_note-ars-oraclelawsuitwin-231"><a href="#cite_ref-ars-oraclelawsuitwin_231-0">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://arstechnica.com/information-technology/2012/08/hp-wins-judgement-in-itanium-suit-against-oracle/">"HP wins judgment in Itanium suit against Oracle"</a>. Ars Technica. August 2012. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20201112030259/https://arstechnica.com/information-technology/2012/08/hp-wins-judgement-in-itanium-suit-against-oracle/">Archived</a> from the original on November 12, 2020. Retrieved July 1, 2016.</cite>

</li>

<li id="cite_note-ars-itaniumlawsuit-232"><a href="#cite_ref-ars-itaniumlawsuit_232-0">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://arstechnica.com/information-technology/2016/06/hp-awarded-3b-in-damages-from-oracle-over-itanium-database-cancellation/">"HP awarded $3B in damages from Oracle over Itanium database cancelation"</a>. Ars Technica. July 2016. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20201108090154/https://arstechnica.com/information-technology/2016/06/hp-awarded-3b-in-damages-from-oracle-over-itanium-database-cancellation/">Archived</a> from the original on November 8, 2020. Retrieved July 1, 2016.</cite>

</li>

<li id="cite_note-bloomberg-itanium3b-233"><a href="#cite_ref-bloomberg-itanium3b_233-0">^</a> <cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://www.bloomberg.com/news/articles/2016-06-30/oracle-ordered-to-pay-hp-3-billion-by-jury-for-itanium-damages">"Oracle Loses $3 Million Verdict For Ditching HP Itanium Chip"</a>. Bloomberg.com. 30 June 2016. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160701011939/http://www.bloomberg.com/news/articles/2016-06-30/oracle-ordered-to-pay-hp-3-billion-by-jury-for-itanium-damages">Archived</a> from the original on 2016-07-01. Retrieved July 1, 2016.</cite>

</li>

<li id="cite_note-reuters-oracle-234"><a href="#cite_ref-reuters-oracle_234-0">^</a> <cite id="CITEREFBrittain2021" class="citation news cs1">Brittain, Blake (15 June 2021). <a rel="nofollow" class="external text" href="https://www.reuters.com/legal/transactional/oracle-loses-bid-upend-hps-3-billion-win-2021-06-14/">"Oracle loses bid to upend HP's $3 billion win"</a>. Reuters. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20210709191923/https://www.reuters.com/legal/transactional/oracle-loses-bid-upend-hps-3-billion-win-2021-06-14/">Archived</a> from the original on 2021-07-09. Retrieved July 7, 2021.</cite>

</li>

<li id="cite_note-235"><a href="#cite_ref-235">^</a> <cite id="CITEREFVance2009" class="citation news cs1"><a href="Ashlee_Vance" title="Ashlee Vance">Vance, Ashlee</a> (May 21, 2009). <a rel="nofollow" class="external text" href="https://bits.blogs.nytimes.com/2009/11/17/a-decade-later-intels-itanium-chip-makes-a-profit/">"A Decade Later, Intel's Itanium Chip Makes a Profit"</a>. <a href="The_New_York_Times" title="The New York Times">The New York Times</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20111104141808/http://bits.blogs.nytimes.com/2009/11/17/a-decade-later-intels-itanium-chip-makes-a-profit/">Archived</a> from the original on November 4, 2011. Retrieved April 7, 2010.</cite>

</li>

<li id="cite_note-Intel_Itanium_Commitment-236"><a href="#cite_ref-Intel_Itanium_Commitment_236-0">^</a> <cite id="CITEREFDarling2011" class="citation web cs1">Darling, Patrick (March 23, 2011). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200327004812/https://newsroom.intel.com/chip-shots/chip-shot-intel-reaffirms-commitment-to-itanium/#gs.6ytayt">"Intel Reaffirms Commitment to Itanium"</a>. Chip Shots. Intel. Archived from <a rel="nofollow" class="external text" href="https://newsroom.intel.com/chip-shots/chip-shot-intel-reaffirms-commitment-to-itanium/#gs.6ytayt">the original</a> on March 27, 2020. Retrieved May 20, 2020.</cite>

</li>

<li id="cite_note-237"><a href="#cite_ref-237">^</a> <cite id="CITEREFManek_Dubash2006" class="citation web cs1">Manek Dubash (July 20, 2006). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110219212053/http://features.techworld.com/operating-systems/2690/will-intel-abandon-the-itanium/">"Will Intel abandon the Itanium?"</a>. <a href="Techworld" class="mw-redirect" title="Techworld">Techworld</a>. Archived from <a rel="nofollow" class="external text" href="http://features.techworld.com/operating-systems/2690/will-intel-abandon-the-itanium/">the original</a> on February 19, 2011. Retrieved December 19, 2010. <q>Once touted by Intel as a replacement for the x86 product line, expectations for Itanium have been throttled well back.</q></cite>

</li>

<li id="cite_note-238"><a href="#cite_ref-238">^</a> <cite id="CITEREFDemerjian2003" class="citation web cs1 cs1-prop-unfit">Demerjian, Charlie (September 26, 2003). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20091010181925/http://www.theinquirer.net/inquirer/news/1029651/why-intels-prescott-will-use-amd64--extensions">"Why Intel's Prescott will use AMD64 extensions"</a>. <a href="The_Inquirer" title="The Inquirer">The Inquirer</a>. Archived from the original on October 10, 2009. Retrieved October 7, 2009.</cite>

</li>

</ol></div>

<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

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<ul><li><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/series/451/intel-itanium-processor.html">Intel Itanium Processor Product Specifications</a></li>

<li><a rel="nofollow" class="external text" href="https://www.hpe.com/us/en/servers/hp-ux.html#portfolio">HPE Integrity Servers</a> official web page</li>

<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20070223234225/http://www.gelato.unsw.edu.au/IA64wiki/ItaniumInternals">Some undocumented Itanium 2 microarchitectural information</a></li>

<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110706223150/http://sverre.web.cern.ch/sverre/IA64_1.pdf">IA-64 tutorial, including code examples</a> at the <a href="Wayback_Machine" title="Wayback Machine">Wayback Machine</a> (archived July 6, 2011)</li>

<li><a rel="nofollow" class="external text" href="https://archive.today/20130103063317/http://www.hp.com/go/integrity">Itanium Docs at HP</a></li>

<li><a rel="nofollow" class="external text" href="https://people.computing.clemson.edu/~mark/epic.html">Historical background for EPIC instruction set architectures</a></li></ul>

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</style><div id="Intel_processors144" style="font-size:114%;margin:0 4em"><a href="List_of_Intel_processors" title="List of Intel processors">Intel processors</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="List_of_Intel_processors" title="List of Intel processors">Processors</a>

<li><a href="List_of_Intel_Celeron_processors" title="List of Intel Celeron processors">Celeron</a></li>

<li><a href="List_of_Intel_Pentium_processors" title="List of Intel Pentium processors">Pentium</a>

<li><a href="Intel_Quark#List_of_Intel_Quark_processors" title="Intel Quark">Quark</a></li>

<li><a href="List_of_Intel_Itanium_processors" title="List of Intel Itanium processors">Itanium</a></li></ul></li>

<li><a href="List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></li>

<li><a href="List_of_Intel_chipsets" title="List of Intel chipsets">Chipsets</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="IA-32" title="IA-32">IA-32</a> (<a href="32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Pentium_M" title="Pentium M">P6 variant (Pentium M)</a></li>

<li><a href="Yonah_(microprocessor)" title="Yonah (microprocessor)">P6 variant (Enhanced Pentium M)</a></li></ul></li>

<li><a href="NetBurst" title="NetBurst">NetBurst</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="X86-64" title="X86-64">x86-64</a> (<a href="64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Penryn_(microarchitecture)" title="Penryn (microarchitecture)">Penryn</a></li></ul></li>

<li><a href="Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a>

<ul><li><a href="Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a></li></ul></li>

<li><a href="Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a>

<ul><li><a href="Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a></li></ul></li>

<li><a href="Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a>

<ul><li><a href="Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a></li></ul></li>

<li><a href="Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a>

<ul><li><a href="Cannon_Lake_(microprocessor)" title="Cannon Lake (microprocessor)">Cannon Lake</a></li></ul></li>

<li><a href="Sunny_Cove_(microarchitecture)" title="Sunny Cove (microarchitecture)">Sunny Cove</a>

<ul><li><a href="Cypress_Cove_(microarchitecture)" class="mw-redirect" title="Cypress Cove (microarchitecture)">Cypress Cove</a></li></ul></li>

<li><a href="Willow_Cove" title="Willow Cove">Willow Cove</a></li>

<li><a href="Golden_Cove" title="Golden Cove">Golden Cove</a>

<ul><li><a href="Raptor_Cove" class="mw-redirect" title="Raptor Cove">Raptor Cove</a></li></ul></li>

<li>Redwood Cove</li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="X86" title="X86">x86</a> <a href="Ultra-low-voltage_processor" title="Ultra-low-voltage processor">ULV</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Bonnell_(microarchitecture)" title="Bonnell (microarchitecture)">Bonnell</a>

<ul><li><a href="Saltwell_(microarchitecture)" class="mw-redirect" title="Saltwell (microarchitecture)">Saltwell</a></li>

<li><a href="Silvermont" title="Silvermont">Silvermont</a></li></ul></li>

<li><a href="Goldmont" title="Goldmont">Goldmont</a>

<ul><li><a href="Goldmont_Plus" title="Goldmont Plus">Goldmont Plus</a></li></ul></li>

<li><a href="Tremont_(microarchitecture)" title="Tremont (microarchitecture)">Tremont</a>

<ul><li><a href="Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a></li></ul></li>

<li>Crestmont</li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Current products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="x86-64_(64-bit)40" scope="row" class="navbox-group" style="width:8.5em"><a href="X86-64" title="X86-64">x86-64</a> (<a href="64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="padding:0"><div style="padding:0 0.25em">

<li><a href="Celeron" title="Celeron">Celeron</a></li>

<li><a href="Pentium" title="Pentium">Pentium</a></li>

<li><a href="Intel_Core#Core_and_Core_Ultra_3/5/7/9" title="Intel Core">Core Ultra</a>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Discontinued</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Binary-coded_decimal" title="Binary-coded decimal">BCD</a> oriented (<a href="4-bit_computing" title="4-bit computing">4-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">pre-x86 (<a href="8-bit_computing" title="8-bit computing">8-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Early <a href="X86" title="X86">x86</a> (<a href="16-bit_computing" title="16-bit computing">16-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="X87" title="X87">x87</a> (external <a href="Floating-point_unit" title="Floating-point unit">FPUs</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<dl><dt>8/16-bit databus</dt>

<dt>16-bit databus</dt>

<dt>32-bit databus</dt>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="IA-32" title="IA-32">IA-32</a> (<a href="32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="RapidCAD" title="RapidCAD">RapidCAD</a></li>

<li><a href="I486_OverDrive" title="I486 OverDrive">OverDrive</a></li></ul></li>

<li><a href="Celeron" title="Celeron">Celeron</a> (1998)

<li><a href="Pentium" title="Pentium">Pentium</a>

<ul><li><a href="Pentium_(original)" title="Pentium (original)">Original i586</a></li>

<li><a href="Pentium_OverDrive" title="Pentium OverDrive">OverDrive</a></li>

<ul><li><a href="List_of_Intel_P6-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel P6-based Xeon microprocessors">P6-based</a></li>

<li><a href="List_of_Intel_NetBurst-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">NetBurst-based</a></li>

<li><a href="List_of_Intel_Core-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">Core-based</a></li></ul></li>

<li><a href="Intel_Quark" title="Intel Quark">Quark</a></li>

<li><a href="Tolapai" title="Tolapai">Tolapai</a></li></ul>

<li><a href="Celeron" title="Celeron">Celeron</a>

<li><a href="Pentium" title="Pentium">Pentium</a>

<li><a href="Pentium_D#Smithfield_XE" title="Pentium D">Extreme Edition</a></li>

<ul><li><a href="List_of_Intel_Xeon_processors_(Nehalem-based)" title="List of Intel Xeon processors (Nehalem-based)">Nehalem-based</a></li>

<li><a href="List_of_Intel_Xeon_processors_(Sandy_Bridge-based)" title="List of Intel Xeon processors (Sandy Bridge-based)">Sandy Bridge-based</a></li>

<li><a href="List_of_Intel_Xeon_processors_(Ivy_Bridge-based)" title="List of Intel Xeon processors (Ivy Bridge-based)">Ivy Bridge-based</a></li>

<li><a href="List_of_Intel_Xeon_processors_(Haswell-based)" title="List of Intel Xeon processors (Haswell-based)">Haswell-based</a></li>

<li><a href="List_of_Intel_Xeon_processors_(Broadwell-based)" title="List of Intel Xeon processors (Broadwell-based)">Broadwell-based</a></li>

<li><a href="List_of_Intel_Xeon_processors_(Skylake-based)" title="List of Intel Xeon processors (Skylake-based)">Skylake-based</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<dd><a href="StrongARM" title="StrongARM">StrongARM</a></dd>

<dd><a href="XScale" title="XScale">XScale</a></dd></dl>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li>

<li><a href="Process%E2%80%93architecture%E2%80%93optimization_model" title="Process–architecture–optimization model">Process–architecture–optimization model</a></li>

<li><a href="List_of_Intel_graphics_processing_units" title="List of Intel graphics processing units">Intel GPUs</a>

<li><a href="Intel_Graphics_Technology" title="Intel Graphics Technology">Intel HD, UHD, and Iris Graphics</a></li>

<li><a href="PCI_IDE_ISA_Xcelerator" class="mw-redirect" title="PCI IDE ISA Xcelerator">PIIXs</a></li>

<li><a href="Stratix" title="Stratix">Stratix</a></li>

<li><a href="List_of_Intel_codenames" title="List of Intel codenames">Codenames</a></li>

<li><a href="Larrabee_(microarchitecture)" title="Larrabee (microarchitecture)">Larrabee</a></li></ul>

</div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox" aria-labelledby="Processor_technologies439" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Processor_technologies439" style="font-size:114%;margin:0 4em"><a href="Processor_(computing)" title="Processor (computing)">Processor technologies</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Model_of_computation" title="Model of computation">Models</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Abstract_machine" title="Abstract machine">Abstract machine</a></li>

<li><a href="Stored-program_computer" title="Stored-program computer">Stored-program computer</a></li>

<li><a href="Finite-state_machine" title="Finite-state machine">Finite-state machine</a>

<ul><li><a href="Finite-state_machine_with_datapath" class="mw-redirect" title="Finite-state machine with datapath">with datapath</a></li>

<li><a href="Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical</a></li>

<li><a href="Deterministic_finite_automaton" title="Deterministic finite automaton">Deterministic finite automaton</a></li>

<li><a href="Queue_automaton" title="Queue automaton">Queue automaton</a></li>

<li><a href="Cellular_automaton" title="Cellular automaton">Cellular automaton</a></li>

<li><a href="Quantum_cellular_automaton" title="Quantum cellular automaton">Quantum cellular automaton</a></li></ul></li>

<li><a href="Turing_machine" title="Turing machine">Turing machine</a>

<ul><li><a href="Alternating_Turing_machine" title="Alternating Turing machine">Alternating Turing machine</a></li>

<li><a href="Universal_Turing_machine" title="Universal Turing machine">Universal</a></li>

<li><a href="Post%E2%80%93Turing_machine" title="Post–Turing machine">Post–Turing</a></li>

<li><a href="Quantum_Turing_machine" title="Quantum Turing machine">Quantum</a></li>

<li><a href="Nondeterministic_Turing_machine" title="Nondeterministic Turing machine">Nondeterministic Turing machine</a></li>

<li><a href="Probabilistic_Turing_machine" title="Probabilistic Turing machine">Probabilistic Turing machine</a></li>

<li><a href="Hypercomputation" title="Hypercomputation">Hypercomputation</a></li>

<li><a href="Zeno_machine" title="Zeno machine">Zeno machine</a></li></ul></li>

<li><a href="History_of_general-purpose_CPUs#Belt_machine_architecture" title="History of general-purpose CPUs">Belt machine</a></li>

<li><a href="Stack_machine" title="Stack machine">Stack machine</a></li>

<li><a href="Register_machine" title="Register machine">Register machines</a>

<ul><li><a href="Counter_machine" title="Counter machine">Counter</a></li>

<li><a href="Pointer_machine" title="Pointer machine">Pointer</a></li>

<li><a href="Random-access_machine" title="Random-access machine">Random-access</a></li>

<li><a href="Random-access_stored-program_machine" title="Random-access stored-program machine">Random-access stored program</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_architecture" title="Computer architecture">Architecture</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Microarchitecture" title="Microarchitecture">Microarchitecture</a></li>

<li><a href="Von_Neumann_architecture" title="Von Neumann architecture">Von Neumann</a></li>

<li><a href="Harvard_architecture" title="Harvard architecture">Harvard</a>

<ul><li><a href="Modified_Harvard_architecture" title="Modified Harvard architecture">modified</a></li></ul></li>

<li><a href="Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li>

<li><a href="Transport_triggered_architecture" title="Transport triggered architecture">Transport-triggered</a></li>

<li><a href="Cellular_architecture" title="Cellular architecture">Cellular</a></li>

<li><a href="Endianness" title="Endianness">Endianness</a></li>

<li><a href="Computer_data_storage" title="Computer data storage">Memory access</a>

<li><a href="Load%E2%80%93store_architecture" title="Load–store architecture">Load–store</a></li>

<li><a href="Register%E2%80%93memory_architecture" title="Register–memory architecture">Register/memory</a></li></ul></li>

<li><a href="Cache_hierarchy" title="Cache hierarchy">Cache hierarchy</a></li>

<li><a href="Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a>

<ul><li><a href="Virtual_memory" title="Virtual memory">Virtual memory</a></li>

<li><a href="Secondary_storage" class="mw-redirect" title="Secondary storage">Secondary storage</a></li></ul></li>

<li><a href="Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">Heterogeneous</a></li>

<li><a href="Fabric_computing" title="Fabric computing">Fabric</a></li>

<li><a href="Multiprocessing" title="Multiprocessing">Multiprocessing</a></li>

<li><a href="Cognitive_computing" title="Cognitive computing">Cognitive</a></li>

<li><a href="Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_set_architecture" title="Instruction set architecture">Instruction set architectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Types</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Orthogonal_instruction_set" title="Orthogonal instruction set">Orthogonal instruction set</a></li>

<li><a href="Application-specific_instruction_set_processor" title="Application-specific instruction set processor">Application-specific</a></li>

<ul><li><a href="TRIPS_architecture" title="TRIPS architecture">TRIPS</a></li></ul></li>

<li><a href="VISC_architecture" title="VISC architecture">VISC architecture</a></li>

<li><a href="Quantum_computing" title="Quantum computing">Quantum computing</a></li>

<li><a href="Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison</a>

<ul><li><a href="Addressing_mode" title="Addressing mode">Addressing modes</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Instruction sets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Motorola_68000_series" title="Motorola 68000 series">Motorola 68000 series</a></li>

<li><a href="Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li>

<li>Power

<ul><li><a href="IBM_POWER_architecture" title="IBM POWER architecture">POWER</a></li>

<li><a href="PowerPC" title="PowerPC">PowerPC</a></li>

<li><a href="Power_ISA" title="Power ISA">Power ISA</a></li></ul></li>

<li><a href="Clipper_architecture" title="Clipper architecture">Clipper architecture</a></li>

<li><a href="SPARC" title="SPARC">SPARC</a></li>

<li><a href="SuperH" title="SuperH">SuperH</a></li>

<li><a href="DEC_Alpha" title="DEC Alpha">DEC Alpha</a></li>

<li><a href="ETRAX_CRIS" title="ETRAX CRIS">ETRAX CRIS</a></li>

<li><a href="Unicore" title="Unicore">Unicore</a></li>

<li><a href="IA-64" title="IA-64">Itanium</a></li>

<li><a href="OpenRISC" title="OpenRISC">OpenRISC</a></li>

<li><a href="MicroBlaze" title="MicroBlaze">MicroBlaze</a></li>

<li>System/3x0

<li><a href="Z/Architecture" title="Z/Architecture">z/Architecture</a></li></ul></li>

<li>Tilera ISA</li>

<li><a href="VISC_architecture" title="VISC architecture">VISC architecture</a></li>

<li><a href="Adapteva" class="mw-redirect" title="Adapteva">Epiphany architecture</a></li>

<li><a href="Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Others</a></li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_cycle" title="Instruction cycle">Execution</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_pipelining" title="Instruction pipelining">Instruction pipelining</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Pipeline_stall" title="Pipeline stall">Pipeline stall</a></li>

<li><a href="Operand_forwarding" title="Operand forwarding">Operand forwarding</a></li>

<li><a href="Classic_RISC_pipeline" title="Classic RISC pipeline">Classic RISC pipeline</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hazard_(computer_architecture)" title="Hazard (computer architecture)">Hazards</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Data_dependency" title="Data dependency">Data dependency</a></li>

<li><a href="Structural_hazard" class="mw-redirect" title="Structural hazard">Structural</a></li>

<li><a href="Control_hazard" class="mw-redirect" title="Control hazard">Control</a></li>

<li><a href="False_sharing" title="False sharing">False sharing</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Out-of-order_execution" title="Out-of-order execution">Out-of-order</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Scoreboarding" title="Scoreboarding">Scoreboarding</a></li>

<li><a href="Tomasulo's_algorithm" title="Tomasulo's algorithm">Tomasulo's algorithm</a>

<ul><li><a href="Reservation_station" title="Reservation station">Reservation station</a></li>

<li><a href="Re-order_buffer" title="Re-order buffer">Re-order buffer</a></li></ul></li>

<li><a href="Register_renaming" title="Register renaming">Register renaming</a></li>

<li><a href="Wide-issue" title="Wide-issue">Wide-issue</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Speculative_execution" title="Speculative execution">Speculative</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Branch_predictor" title="Branch predictor">Branch prediction</a></li>

<li><a href="Memory_dependence_prediction" title="Memory dependence prediction">Memory dependence prediction</a></li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Parallel_computing" title="Parallel computing">Parallelism</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Level</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Bit-serial_architecture" title="Bit-serial architecture">Bit-serial</a></li>

<li><a href="Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li>

<li><a href="Instruction_pipelining" title="Instruction pipelining">Pipelining</a>

<ul><li><a href="Scalar_processor" title="Scalar processor">Scalar</a></li>

<li><a href="Superscalar_processor" title="Superscalar processor">Superscalar</a></li></ul></li>

<ul><li><a href="Thread_(computing)" title="Thread (computing)">Thread</a></li>

<li><a href="Process_(computing)" title="Process (computing)">Process</a></li></ul></li>

<ul><li><a href="Vector_processor" title="Vector processor">Vector</a></li></ul></li>

<li><a href="Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li>

<li><a href="Distributed_architecture" class="mw-redirect" title="Distributed architecture">Distributed</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Temporal_multithreading" title="Temporal multithreading">Temporal</a></li>

<li><a href="Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a>

<ul><li><a href="Hyper-threading" title="Hyper-threading">Hyperthreading</a></li>

<li><a href="Simultaneous_and_heterogeneous_multithreading" title="Simultaneous and heterogeneous multithreading">Simultaneous and heterogenous</a></li></ul></li>

<li><a href="Speculative_multithreading" title="Speculative multithreading">Speculative</a></li>

<li><a href="Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li>

<li><a href="Cooperative_multitasking" title="Cooperative multitasking">Cooperative</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Flynn's_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Single_instruction%2C_multiple_threads" title="Single instruction, multiple threads">Array processing (SIMT)</a></li>

<li><a href="Flynn's_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing</a></li>

<li><a href="Flynn's_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing</a></li>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_performance" title="Computer performance">Processor performance</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Transistor_count" title="Transistor count">Transistor count</a></li>

<li><a href="Instructions_per_cycle" title="Instructions per cycle">Instructions per cycle</a> (IPC)

<ul><li><a href="Cycles_per_instruction" title="Cycles per instruction">Cycles per instruction</a> (CPI)</li></ul></li>

<li><a href="Instructions_per_second" title="Instructions per second">Instructions per second</a> (IPS)</li>

<li><a href="FLOPS" class="mw-redirect" title="FLOPS">Floating-point operations per second</a> (FLOPS)</li>

<li><a href="Transactions_per_second" title="Transactions per second">Transactions per second</a> (TPS)</li>

<li><a href="SUPS" title="SUPS">Synaptic updates per second</a> (SUPS)</li>

<li><a href="Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li>

<li><a href="Cache_performance_measurement_and_metric" title="Cache performance measurement and metric">Cache performance metrics</a></li>

<li><a href="Computer_performance_by_orders_of_magnitude" title="Computer performance by orders of magnitude">Computer performance by orders of magnitude</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Processor_(computing)" title="Processor (computing)">Types</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Central_processing_unit" title="Central processing unit">Central processing unit</a> (CPU)</li>

<li><a href="Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)

<ul><li><a href="General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li></ul></li>

<li><a href="Vector_processor" title="Vector processor">Vector</a></li>

<li><a href="Barrel_processor" title="Barrel processor">Barrel</a></li>

<li><a href="Stream_processing" title="Stream processing">Stream</a></li>

<li><a href="Tile_processor" title="Tile processor">Tile processor</a></li>

<li><a href="Coprocessor" title="Coprocessor">Coprocessor</a></li>

<li><a href="Multi-chip_module" title="Multi-chip module">Multi-chip module</a> (MCM)</li>

<li><a href="System_in_a_package" title="System in a package">System in a package</a> (SiP)</li>

<li><a href="Package_on_a_package" title="Package on a package">Package on a package</a> (PoP)</li></ul>

</div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">By application</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Embedded_system" title="Embedded system">Embedded system</a></li>

<li><a href="Microprocessor" title="Microprocessor">Microprocessor</a></li>

<li><a href="Microcontroller" title="Microcontroller">Microcontroller</a></li>

<li><a href="Mobile_processor" title="Mobile processor">Mobile</a></li>

<li><a href="Ultra-low-voltage_processor" title="Ultra-low-voltage processor">Ultra-low-voltage</a></li>

<li><a href="Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Systems on chip</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="System_on_a_chip" title="System on a chip">System on a chip</a> (SoC)</li>

<li><a href="Multiprocessor_system_on_a_chip" class="mw-redirect" title="Multiprocessor system on a chip">Multiprocessor</a> (MPSoC)</li>

<li><a href="Cypress_PSoC" title="Cypress PSoC">Cypress PSoC</a></li>

<li><a href="Network_on_a_chip" title="Network on a chip">Network on a chip</a> (NoC)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_acceleration" title="Hardware acceleration">Hardware accelerators</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Coprocessor" title="Coprocessor">Coprocessor</a></li>

<li><a href="AI_accelerator" class="mw-redirect" title="AI accelerator">AI accelerator</a></li>

<li><a href="Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)</li>

<li><a href="Image_processor" title="Image processor">Image processor</a></li>

<li><a href="Vision_processing_unit" title="Vision processing unit">Vision processing unit</a> (VPU)</li>

<li><a href="Physics_processing_unit" title="Physics processing unit">Physics processing unit</a> (PPU)</li>

<li><a href="Digital_signal_processor" title="Digital signal processor">Digital signal processor</a> (DSP)</li>

<li><a href="Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li>

<li><a href="Secure_cryptoprocessor" title="Secure cryptoprocessor">Secure cryptoprocessor</a></li>

<li><a href="Network_processor" title="Network processor">Network processor</a></li>

<li><a href="Baseband_processor" title="Baseband processor">Baseband processor</a></li></ul>

</div></td></tr></tbody></table><div>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Word_(computer_architecture)" title="Word (computer architecture)">Word size</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Bit_slicing" title="Bit slicing">bit slicing</a></li>

<li><a href="Word_(computer_architecture)#Table_of_word_sizes" title="Word (computer architecture)">others</a>

<ul><li><a href="Word_(computer_architecture)#Variable-word_architectures" title="Word (computer architecture)">variable</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Core count</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Single-core" title="Single-core">Single-core</a></li>

<li><a href="Multi-core_processor" title="Multi-core processor">Multi-core</a></li>

<li><a href="Manycore_processor" title="Manycore processor">Manycore</a></li>

<li><a href="Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous architecture</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Cache_(computing)" title="Cache (computing)">Cache</a>

<ul><li><a href="CPU_cache" title="CPU cache">CPU cache</a></li>

<li><a href="Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li>

<li><a href="Data_cache" class="mw-redirect" title="Data cache">Data cache</a></li>

<li><a href="Instruction_cache" class="mw-redirect" title="Instruction cache">Instruction cache</a></li>

<li><a href="Cache_replacement_policies" title="Cache replacement policies">replacement policies</a></li>

<li><a href="Cache_coherence" title="Cache coherence">coherence</a></li></ul></li>

<li><a href="Clock_rate" title="Clock rate">Clock rate</a></li>

<li><a href="Clock_signal" title="Clock signal">Clock signal</a></li>

</div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Execution_unit" title="Execution unit">Functional units</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Arithmetic_logic_unit" title="Arithmetic logic unit">Arithmetic logic unit</a> (ALU)</li>

<li><a href="Address_generation_unit" title="Address generation unit">Address generation unit</a> (AGU)</li>

<li><a href="Floating-point_unit" title="Floating-point unit">Floating-point unit</a> (FPU)</li>

<li><a href="Memory_management_unit" title="Memory management unit">Memory management unit</a> (MMU)

<ul><li><a href="Load%E2%80%93store_unit" title="Load–store unit">Load–store unit</a></li>

<li><a href="Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB)</li></ul></li>

<li><a href="Branch_predictor" title="Branch predictor">Branch predictor</a></li>

<li><a href="Branch_target_predictor" title="Branch target predictor">Branch target predictor</a></li>

<li><a href="Memory_controller" title="Memory controller">Integrated memory controller</a> (IMC)

<ul><li><a href="Memory_management_unit" title="Memory management unit">Memory management unit</a></li></ul></li>

<li><a href="Instruction_decoder" class="mw-redirect" title="Instruction decoder">Instruction decoder</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Logic_gate" title="Logic gate">Logic</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Combinational_logic" title="Combinational logic">Combinational</a></li>

<li><a href="Sequential_logic" title="Sequential logic">Sequential</a></li>

<li><a href="Logic_gate" title="Logic gate">Logic gate</a>

<ul><li><a href="Quantum_logic_gate" title="Quantum logic gate">Quantum</a></li>

<li><a href="Gate_array" title="Gate array">Array</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_register" title="Hardware register">Registers</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Processor_register" title="Processor register">Processor register</a></li>

<li><a href="Status_register" title="Status register">Status register</a></li>

<li><a href="Stack_register" title="Stack register">Stack register</a></li>

<li><a href="Register_file" title="Register file">Register file</a></li>

<li><a href="Memory_buffer_register" title="Memory buffer register">Memory buffer</a></li>

<li><a href="Memory_address_register" title="Memory address register">Memory address register</a></li>

<li><a href="Program_counter" title="Program counter">Program counter</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Control_unit" title="Control unit">Control unit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Hardwired_control_unit" class="mw-redirect" title="Hardwired control unit">Hardwired control unit</a></li>

<li><a href="Instruction_unit" title="Instruction unit">Instruction unit</a></li>

<li><a href="Data_buffer" title="Data buffer">Data buffer</a></li>

<li><a href="Write_buffer" title="Write buffer">Write buffer</a></li>

<li><a href="Microcode" title="Microcode">Microcode</a> <a href="ROM_image" title="ROM image">ROM</a></li>

<li><a href="Counter_(digital)" title="Counter (digital)">Counter</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Datapath" title="Datapath">Datapath</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Multiplexer" title="Multiplexer">Multiplexer</a></li>

<li><a href="Demultiplexer" class="mw-redirect" title="Demultiplexer">Demultiplexer</a></li>

<li><a href="Adder_(electronics)" title="Adder (electronics)">Adder</a></li>

<li><a href="Binary_multiplier" title="Binary multiplier">Multiplier</a>

<li><a href="Binary_decoder" title="Binary decoder">Binary decoder</a>

<ul><li><a href="Address_decoder" title="Address decoder">Address decoder</a></li>

<li><a href="Sum-addressed_decoder" title="Sum-addressed decoder">Sum-addressed decoder</a></li></ul></li>

<li><a href="Barrel_shifter" title="Barrel shifter">Barrel shifter</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Electronic_circuit" title="Electronic circuit">Circuitry</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Integrated_circuit" title="Integrated circuit">Integrated circuit</a>

<li><a href="Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal</a></li>

<li><a href="Power_management_integrated_circuit" title="Power management integrated circuit">Power management</a></li></ul></li>

<li><a href="Boolean_circuit" title="Boolean circuit">Boolean</a></li>

<li><a href="Circuit_(computer_science)" title="Circuit (computer science)">Digital</a></li>

<li><a href="Analogue_electronics" title="Analogue electronics">Analog</a></li>

<li><a href="Quantum_circuit" title="Quantum circuit">Quantum</a></li>

<li><a href="Switch#Electronic_switches" title="Switch">Switch</a></li></ul>

</div></td></tr></tbody></table><div>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Power_management" title="Power management">Power management</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Dynamic_frequency_scaling" title="Dynamic frequency scaling">Dynamic frequency scaling</a></li>

<li><a href="Dynamic_voltage_scaling" title="Dynamic voltage scaling">Dynamic voltage scaling</a></li>

<li><a href="Clock_gating" title="Clock gating">Clock gating</a></li>

<li><a href="Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="History_of_general-purpose_CPUs" title="History of general-purpose CPUs">History of general-purpose CPUs</a></li>

<li><a href="Microprocessor_chronology" title="Microprocessor chronology">Microprocessor chronology</a></li>

<li><a href="Processor_design" title="Processor design">Processor design</a></li>

<li><a href="Digital_electronics" title="Digital electronics">Digital electronics</a></li>

<li><a href="Hardware_security_module" title="Hardware security module">Hardware security module</a></li>

<li><a href="Semiconductor_device_fabrication" title="Semiconductor device fabrication">Semiconductor device fabrication</a></li>

<li><a href="Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li>

<li><a href="Pin_grid_array" title="Pin grid array">Pin grid array</a></li>

<li><a href="Chip_carrier" title="Chip carrier">Chip carrier</a></li></ul>

</div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox" aria-labelledby="Hewlett-Packard1228" style="padding:3px"><table class="nowraplinks hlist mw-collapsible mw-collapsed navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="3"><div id="Hewlett-Packard1228" style="font-size:114%;margin:0 4em"><a href="Hewlett-Packard" title="Hewlett-Packard">Hewlett-Packard</a></div></th></tr><tr><td class="navbox-abovebelow" colspan="3"><div>

<ul><li>Split into <a href="HP_Inc." title="HP Inc.">HP Inc.</a> and <a href="Hewlett_Packard_Enterprise" title="Hewlett Packard Enterprise">Hewlett Packard Enterprise</a> in 2015</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="List_of_Hewlett-Packard_products" title="List of Hewlett-Packard products">Products</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Personal computers</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="List_of_HP_business_desktops" title="List of HP business desktops">Desktops</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="HP_Blackbird_002" title="HP Blackbird 002">Blackbird 002</a></li>

<li><a href="Compaq" title="Compaq">Compaq series</a>

<li><a href="HP_Compaq" class="mw-redirect" title="HP Compaq">HP Compaq</a></li>

<li><a href="Compaq_Presario" title="Compaq Presario">Presario</a></li></ul></li>

<li><a href="List_of_HP_business_desktops" title="List of HP business desktops">EliteDesk</a></li>

<li><a href="HP_Pavilion" title="HP Pavilion">Pavilion</a>*</li>

<li><a href="List_of_HP_business_desktops" title="List of HP business desktops">ProDesk</a></li>

<li><a href="HP_Spectre" title="HP Spectre">Spectre</a></li>

<li><a href="HP_Sprout" title="HP Sprout">Sprout</a></li>

<li><a href="HP_Stream" class="mw-redirect" title="HP Stream">Stream</a></li>

<li><a href="HP_TouchSmart" title="HP TouchSmart">TouchSmart</a></li>

<li><a href="HP_Vectra" title="HP Vectra">Vectra</a></li>

<li><a href="VoodooPC" title="VoodooPC">VoodooPC</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Laptops</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Compaq" title="Compaq">Compaq series</a>

<li><a href="HP_Compaq" class="mw-redirect" title="HP Compaq">HP Compaq</a></li>

<li><a href="Compaq_Presario" title="Compaq Presario">Presario</a></li></ul></li>

<li><a href="HP_EliteBook" title="HP EliteBook">EliteBook</a>*</li>

<li><a href="HP_Essential" title="HP Essential">Essential</a>*</li>

<li><a href="HP_ProBook" title="HP ProBook">ProBook</a>*</li>

<li><a href="HP_OmniBook" title="HP OmniBook">OmniBook</a>*</li>

<li><a href="HP_Pavilion" title="HP Pavilion">Pavilion</a>*

<li><a href="Voodoo_Envy" title="Voodoo Envy">Voodoo Envy</a></li>

<li><a href="HP_ZBook" title="HP ZBook">ZBook</a>*</li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Workstations and servers</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="AlphaServer" title="AlphaServer">AlphaServer</a></li>

<li><a href="HP_Integral_PC" title="HP Integral PC">Integral PC</a></li>

<li><a href="HP_Flexible_Data_Center" title="HP Flexible Data Center">Flexible Data Center</a></li>

<li><a href="HP_Kayak" title="HP Kayak">Kayak</a></li>

<li><a href="HP_Media_Vault" title="HP Media Vault">Media Vault</a></li>

<li><a href="HP_MediaSmart_Server" title="HP MediaSmart Server">MediaSmart Server</a></li>

<li><a href="HP_NetServer" title="HP NetServer">NetServer</a></li>

<li><a href="NonStop_(server_computers)" title="NonStop (server computers)">NonStop</a></li>

<li><a href="HP_Performance_Optimized_Datacenter" title="HP Performance Optimized Datacenter">Performance Optimized Datacenter</a></li>

<li><a href="HP_X-Terminals" title="HP X-Terminals">X-Terminals</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Mobile devices</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Compaq" title="Compaq">Compaq series</a>

<li><a href="HP_calculators" title="HP calculators">Calculators</a>*</li>

<li><a href="HP_Jornada" title="HP Jornada">Jornada</a>

<li><a href="HP_Slate" title="HP Slate">Slate</a>

<li><a href="HP_Slate_500" title="HP Slate 500">Slate 500</a></li></ul></li>

<li><a href="HP_TouchPad" title="HP TouchPad">TouchPad</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Printing and imaging</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="HP_7470" title="HP 7470">7470 Graphics Plotter</a></li>

<li><a href="HP_DeskJet" title="HP DeskJet">DeskJet</a>*</li>

<li><a href="HP_Indigo_Division" title="HP Indigo Division">Indigo</a>*</li>

<li><a href="JetDirect" title="JetDirect">JetDirect</a></li>

<li><a href="HP_LaserJet" title="HP LaserJet">LaserJet</a>*

<li><a href="LightScribe" title="LightScribe">LightScribe</a></li>

<li><a href="HP_Photosmart" title="HP Photosmart">Photosmart</a>

<li><a href="HP_ScanJet" title="HP ScanJet">ScanJet</a>*</li>

<li><a href="Scitex_Vision" title="Scitex Vision">Scitex</a></li>

<li><a href="HP_TopShot" title="HP TopShot">TopShot</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Microprocessors</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Capricorn_(microprocessor)" title="Capricorn (microprocessor)">Capricorn</a></li>

<li><a href="HP_FOCUS" title="HP FOCUS">FOCUS</a></li>

<li><a href="Hewlett-Packard_Nanoprocessor" title="Hewlett-Packard Nanoprocessor">Nanoprocessor</a></li>

<li><a href="HP_Saturn" title="HP Saturn">Saturn</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Computer buses</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="HP_Precision_Bus" title="HP Precision Bus">Precision</a></li>

<li><a href="Runway_bus" title="Runway bus">Runway</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other hardware</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="HP_200A" title="HP 200A">200A Audio Oscillator</a></li>

<li><a href="HP_7935" title="HP 7935">7935 Disc Drive</a></li>

<li><a href="Guardian_Service_Processor" title="Guardian Service Processor">Guardian Service Processor</a></li>

<li><a href="HPE_Integrated_Lights-Out" title="HPE Integrated Lights-Out">Integrated Lights-Out</a>**</li>

<li><a href="HP_Kittyhawk" title="HP Kittyhawk">Kittyhawk</a></li>

<li><a href="HP_Memory_Spot_chip" title="HP Memory Spot chip">Memory Spot</a></li>

<li><a href="NPartition" title="NPartition">nPartition</a>**</li>

<li><a href="ProCurve" title="ProCurve">ProCurve</a></li>

<li><a href="Visualize_EG" title="Visualize EG">Visualize EG</a></li>

<li><a href="HP_xb3000" title="HP xb3000">xb3000 Notebook Expansion Base</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Services</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="HP_ConvergedSystem" title="HP ConvergedSystem">ConvergedSystem</a></li>

<li><a href="HP_Cloud" title="HP Cloud">Cloud</a></li>

<li><a href="HP_CloudSystem" title="HP CloudSystem">CloudSystem</a>**</li>

<li><a href="HPE_Helion" title="HPE Helion">Helion</a>**</li>

<li><a href="MagCloud" title="MagCloud">MagCloud</a>†</li>

<li><a href="Speechbot" title="Speechbot">Speechbot</a></li>

<li><a href="HP_Utility_Data_Center" title="HP Utility Data Center">Utility Data Center</a></li></ul>

</div></td></tr></tbody></table><div></div></td><td class="noviewer navbox-image" rowspan="6" style="width:1px;padding:0 0 0 2px"><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="List_of_Hewlett-Packard_executive_leadership" title="List of Hewlett-Packard executive leadership">CEOs</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Bill_Hewlett" title="Bill Hewlett">Bill Hewlett</a> and <a href="David_Packard" title="David Packard">David Packard</a> (co-founders)</li>

<li><a href="John_A._Young" title="John A. Young">John A. Young</a></li>

<li><a href="Lewis_E._Platt" title="Lewis E. Platt">Lewis E. Platt</a></li>

<li><a href="Carly_Fiorina" title="Carly Fiorina">Carly Fiorina</a></li>

<li><a href="L%C3%A9o_Apotheker" title="Léo Apotheker">Léo Apotheker</a></li>

<li><a href="Meg_Whitman" title="Meg Whitman">Meg Whitman</a> (final CEO)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="List_of_assets_owned_by_HP" title="List of assets owned by HP">Assets</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Ericsson_Hewlett_Packard_Telecom" title="Ericsson Hewlett Packard Telecom">Ericsson Hewlett Packard Telecom</a>†</li>

<li><a href="HP_Garage" title="HP Garage">HP Garage</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="List_of_acquisitions_by_Hewlett-Packard" title="List of acquisitions by Hewlett-Packard">Acquisitions</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Apollo_Computer" title="Apollo Computer">Apollo Computer</a></li>

<li><a href="ArcSight" title="ArcSight">ArcSight</a>†</li>

<li><a href="Aruba_Networks" title="Aruba Networks">Aruba Networks</a>**</li>

<li><a href="Autonomy_Corporation" title="Autonomy Corporation">Autonomy</a>†</li>

<li><a href="Bristol_Technology" title="Bristol Technology">Bristol Technology</a></li>

<li><a href="Compaq" title="Compaq">Compaq</a></li>

<li><a href="Convex_Computer" title="Convex Computer">Convex Computer</a></li>

<li><a href="Colorado_Memory_Systems" title="Colorado Memory Systems">Colorado Memory Systems</a></li>

<li><a href="PathWave_Design" title="PathWave Design">EEsof</a>†</li>

<li><a href="Electronic_Data_Systems" title="Electronic Data Systems">Electronic Data Systems</a>†</li>

<li><a href="Exstream_Software" title="Exstream Software">Exstream Software</a>†</li>

<li><a href="Fortify_Software" title="Fortify Software">Fortify Software</a>†</li>

<li><a href="HP_Indigo_Division" title="HP Indigo Division">Indigo N.V.</a></li>

<li><a href="Knightsbridge_Solutions" title="Knightsbridge Solutions">Knightsbridge Solutions</a></li>

<li><a href="Neoware" title="Neoware">Neoware</a></li>

<li><a href="Opsware" title="Opsware">Opsware</a>†</li>

<li><a href="Mercury_Interactive" title="Mercury Interactive">Mercury Interactive</a>†</li>

<li><a href="Peregrine_Systems" title="Peregrine Systems">Peregrine Systems</a>†</li>

<li><a href="RLX_Technologies" title="RLX Technologies">RLX Technologies</a></li>

<li><a href="Scitex_Vision" title="Scitex Vision">Scitex Vision</a></li>

<li><a href="Snapfish" title="Snapfish">Snapfish</a></li>

<li><a href="Stratavia" title="Stratavia">Stratavia</a></li>

<li><a href="Teradici" title="Teradici">Teradici</a></li>

<li><a href="TOWER_Software" title="TOWER Software">TOWER Software</a></li>

<li><a href="Verifone" title="Verifone">Verifone</a>†</li>

<li><a href="Vertica" title="Vertica">Vertica</a>†</li>

<li><a href="VoodooPC" title="VoodooPC">VoodooPC</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Spin-offs</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Agilent_Technologies" title="Agilent Technologies">Agilent Technologies</a></li>

<li><a href="DXC_Technology" title="DXC Technology">DXC Technology</a></li>

<li><a href="Hewlett_Packard_Enterprise" title="Hewlett Packard Enterprise">Hewlett Packard Enterprise</a></li>

<li><a href="Keysight" title="Keysight">Keysight Technologies</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="HP_Color_Recovery" title="HP Color Recovery">Color Recovery</a></li>

<li><a href="Encompass" title="Encompass">Encompass</a></li>

<li><a href="Hewlett-Packard_Journal" title="Hewlett-Packard Journal">Hewlett-Packard Journal</a></li>

<li><a href="HP-Interex" title="HP-Interex">HP-Interex</a></li>

<li><a href="Rules_of_the_garage" title="Rules of the garage">Rules of the garage</a></li>

<li><a href="Hewlett-Packard_spying_scandal" title="Hewlett-Packard spying scandal">Spying scandal</a></li>

<li><a href="Mission%3A_Space" title="Mission: Space">Mission: SPACE</a></li>

<li><a href="PC_LOAD_LETTER" title="PC LOAD LETTER">PC LOAD LETTER</a></li>

</div></td></tr><tr><td class="navbox-abovebelow" colspan="3"><div>

<ul><li>Asterisk (*) denotes product lines continued by <a href="HP_Inc." title="HP Inc.">HP Inc.</a></li>

<li>Double asterisk (**) denotes product lines and companies now property of <a href="Hewlett_Packard_Enterprise" title="Hewlett Packard Enterprise">Hewlett Packard Enterprise</a></li>

<li>Dagger (†) denotes assets or companies divested and sold off</li></ul>

<ul><li> Hewlett Packard Enterprise</li>

<li> Compaq</li>

<li> HP calculators</li>

<li> HP software</li></ul>

</div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox authority-control" aria-labelledby="Authority_control_databases_frameless&#124;text-top&#124;10px&#124;alt=Edit_this_at_Wikidata&#124;link=https&#58;//www.wikidata.org/wiki/Q390389#identifiers&#124;class=noprint&#124;Edit_this_at_Wikidata823" style="padding:3px"><table class="nowraplinks hlist mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Authority_control_databases_frameless&#124;text-top&#124;10px&#124;alt=Edit_this_at_Wikidata&#124;link=https&#58;//www.wikidata.org/wiki/Q390389#identifiers&#124;class=noprint&#124;Edit_this_at_Wikidata823" style="font-size:114%;margin:0 4em">Authority control databases </div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">National</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"><ul><li><a rel="nofollow" class="external text" href="https://id.loc.gov/authorities/sh2003001198">United States</a></li><li><a rel="nofollow" class="external text" href="https://catalogue.bnf.fr/ark:/12148/cb14617034z">France</a></li><li><a rel="nofollow" class="external text" href="https://data.bnf.fr/ark:/12148/cb14617034z">BnF data</a></li><li><a rel="nofollow" class="external text" href="https://www.nli.org.il/en/authorities/987007537449505171">Israel</a></li></ul></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"><ul><li><a rel="nofollow" class="external text" href="https://lux.collections.yale.edu/view/concept/ffe8554e-e518-49f6-bd04-387fbdbee361">Yale LUX</a></li></ul></div></td></tr></tbody></table></div></div><div><div class="zim-footer">

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